MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof

A method of manufacturing a semiconductor device having a p-channel MOS type field effect transistor and a n-channel MOS type field effect transistor formed on a common semiconductor substrate, comprising the steps of:

• forming a p type transistor forming region for forming said n-channel MOS type field effect transistor and an n type transistor forming region for forming said p-channel MOS type field effect transistor in the main surface of the semiconductor substrate;
• forming a first insulating layer on a surface of said p type and n type transistor forming region;
• forming a polysilicon layer on an upper surface of said first insulating layer;
• patterning said polysilicon layer to form a first gate electrode over said n type transistor forming region and a second gate electrode over said p type transistor forming region;
• covering said p type transistor forming region and said second gate electrode with a first resist;
• implanting a p type impurity into said n type transistor forming region to form first and second low concentration p type impurity regions on opposite sides of said first gate electrode;
• removing said first resist;
• covering said n type transistor forming region and said first gate electrode with a second resist;
• implanting an n type impurity into said p type transistor forming region to form first and second low concentration n type impurity regions on opposite sides of said second gate electrode;
• removing said second resist layer;
• forming a second insulating layer on the first and second gate electrodes and on said first insulating layer adjacent said first and second gate electrodes;
• etching said second insulating layer to form sidewall spaces on opposite sides of each of said first and second gate electrodes;
• covering said n type transistor forming region with a third resist;
• etching said sidewall spacers formed on the sidewalls of said gate electrode of said p type transistor forming region to reduce a thickness thereof;
• implanting an n type impurity into said p type transistor forming region to form high concentration n type impurity regions on said opposite sides of said second gate electrode;
• removing said third resist;
• covering said p type transistor region with a fourth resist;
• and
• implanting a p type impurity into said n type transistor forming region to form high concentration p type impurity regions on said opposite sides of said first gate electrode.