Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods

A process for the simultaneous fabrication of a first insulated-gate field-effect transistor and a second insulated-gate field-effect transistor at a face of a semiconductor layer having a first conductivity type, comprising the steps of:

• simultaneously forming first and second tank regions in said semiconductor layer to be of a second conductivity type opposite said first conductivity type and to be spaced from each other;
• simultaneously forming third and fourth tank regions to be of said first conductivity type, said third tank region formed within said first tank region, said fourth tank region formed within said second tank region;
• forming a back gate region of said first conductivity type to be laterally within said fourth tank region;
• simultaneously forming a conductive control gate to be insulatively disposed over a lateral margin of said third tank region and an annular conductive control gate to be insulatively disposed over a lateral margin of said fourth tank region, said annular control gate disposed laterally outwardly from said back gate region;
• and
• simultaneously forming, to be of said second conductivity type, (a) a highly doped region within said first tank region but spaced from said third tank region, (b) a highly doped region within said third tank region, and (c) a highly doped region within said second tank region but spaced from said fourth tank region, said highly doped regions operable as sources or drains, said third and fourth tank regions functioning as channel regions.