Method of providing lower contact resistance in MOS transistor structures

A method of providing lower contact resistance in the source and drain regions of an MOS transistor, the method comprising the sequential steps of:

• (a) defining regions on a silicon substrate which will later be formed into source and drain regions through the introduction of active dopant species, the future source and drain regions being spaced apart to define a channel region therebetween;
• (b) after defining the future source and drain regions, introducing germanium atoms into the future source and drain regions;
• (c) after introducing germanium atoms into the future source and drain regions, performing an oxidation step to form an oxide layer on the future source and drain regions and to create a germanium-rich layer in the future source and drain regions at the interfacial region between the future source and drain region and the oxide layer;
• and
• (d) after performing the oxidation step, forming an MOS transistor structure having source and drain regions and a gate electrode overlying the channel region and separated therefrom by a layer of dielectric material, wherein the formation of the MOS transistor structure includes the implantation of active dopant species in order to form the source and drain regions.