Method of forming silicon carbide
AssigneeNorthern Telecom Limited
InventorsSing P. Tay, Joseph P. Ellul
Life of this patent
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Abstract
A low temperature CVD method is provided for depositing high quality stoichiometric, poly-crystalline silicon carbide films and for depositing emitter quality, heavily doped silicon carbide films, suitable for application in silicon hetero-junction bipolar transistors. The process is compatible with bipolar-CMOS device processing and comprises pyrolysis of di-tert-butyl silane in an oxygen free ambient, with n-type doping provided by phosphorus source comprising tert-butyl phosphine. Advantageously oxygen is excluded from the reactant gas mixture and the method includes pre-cleaning the susbtrate with nitrogen trifluoride and passivating the silicon carbide film with fluorine species from nitrogen trifluoride.
Claims37
A method of forming silicon carbide for an integrated circuit structure comprising:
- exposing a surface of a substrate in a chemical vapour deposition chamber and purging the chamber to remove residual oxygen by flowing through the chamber an inert gas purified to remove oxygen;
- pre-cleaning and passivating the surface of the substrate with fluorine by exposure to a reactive fluorine containing gas;
- purging the chamber with inert gas;
- then exposing the substrate to a gaseous reactant mixture comprising di-tert-butyl silane and said inert gas and at a controlled flow rate, pressure and at a deposition temperature in the range 550.degree. to 800.degree. C., thereby depositing a layer of silicon carbide on the substrate,
- and subsequently annealing the deposited silicion carbide in an inert atmosphere at a temperature above the deposition temperature and below 1100.degree. C. whereby fluorine is incorporated into and passivates the deposited silicon carbide.
A method of forming a conductive layer of silicon carbide for an integrated circuit structure, comprising:
- exposing a substrate of an integrated circuit within a reaction chamber to a mixture of reactant gases comprising di tert-butyl silane at a flow rate of 250 to 350 sccm and tert-butyl phosphine at a flow rate of 130 to 350 sccm in an inert gas at a flow rate from 200 to 1000 sccm, while maintaining the pressure in the range from 0.25 to 1 Torr and the deposition temperature in the range from 550.degree. to 800.degree. C., thereby depositing a layer of n-doped amorphous silicon carbide on the substrate, and
- annealing the amorphous silicon carbide layer at a temperature above the deposition temperature and below 1100.degree. C. for a time sufficient to form a polycrystalline phase of n-doped silicon carbide.
A method of providing a silicon carbide emitter structure for a silicon heterojuntion bipolar transistor comprising the steps of:
- providing a substrate for an integrated circuit comprising a surface dielectric layer having defined therein an emitter opening, the emitter opening defining an active device region of the substrate including a heavily doped base region;
- exposing the substrate within a reaction chamber;
- purging the chamber with an inert carrier gas to remove residual oxygen;
- and then exposing the substrate to a mixture of reactant gases comprising di-tert-butyl silane at a flow rate of 250 to 350 sccm and tert-butyl phosphine at a flow rate of 130 to 350 sccm in an oxygen free inert carrier gas, at a flow rate from 200 to 1000 sccm, while maintaining the pressure in the range from 0.25 to 1 Torr and the temperature in the range from 550.degree. to 800.degree. C., whereby a layer of n.sup.+ doped amorphous silicon carbide is deposited on the substrate, said layer of silicon carbide comprising less than 0.1 atomic percent oxygen,
- and subsequently annealing the silicon carbide layer in an inert atmosphere at a temperature greater than the deposition temperature and less than 1100.degree. C. and for a time sufficient to form a polycrystalline phase of n.sup.+ doped silicon carbide.
A method of forming polycrystalline silicon carbide for an integrated circuit structure comprising:
- exposing a substrate in a chemical vapour deposition chamber and purging the chamber with an inert gas to remove residual oxygen;
- exposing the substrate to a gaseous reactant mixture comprising di-tert-butyl silane and an oxygen free inert gas, at a controlled flow rate and pressure and at a deposition temperature in the range 550.degree. C. to 800.degree. C., thereby depositing a layer of amorphous silicon carbide on the substrate;
- and
- annealing the deposited amorphous silicon carbide layer in an inert atmosphere at a temperature above the deposition temperature and below 1100.degree. C. for a time sufficient to form polycrystalline silicon carbide.
A method of forming silicon carbide for an integrated circuit, comprising:
- exposing a substrate in a chemical vapour deposition chamber and purging the chamber to remove residual oxygen;
- exposing the substrate to a gaseous reactant mixture comprising di-tert-butyl silane, a source of a dopant species, and an oxygen free inert gas, at a deposition temperature in the range 550.degree. C. to 800.degree. C., and controlling the flow rates and pressure, thereby depositing a layer of silicon carbide on the substrate, the deposited silicon carbide incorporating said dopant species and having an oxygen content of less than 0.1 atomic percent.
A method of forming layer of polycrystalline silicon carbide for an integrated circuit structure comprising:
- exposing a surface of an integrated circuit substrate in a chemical vapour deposition chamber, purging the chamber to remove residual oxygen by flowing through the chamber an inert gas purified to remove oxygen, and then exposing the substrate to a gaseous reactant mixture comprising di-tert-butyl silane, a source of a doping species, and an oxygen free inert gas, at a deposition temperature in the range 550.degree. C. and 800.degree. C., and controlling the pressure and flow rates, thereby depositing a layer of doped amorphous silicon carbide on the substrate;
- and,
- annealing the amorphous silicon carbide layer in an inert atmosphere at a temperature above the deposition temperature and below 1100.degree. C. for a time sufficient to form a conductive layer of doped polycrystalline silicon carbide.
A method of forming silicon carbide for an integrated circuit structure comprising:
- exposing a surface of a substrate of an integrated circuit in a chemical vapour deposition chamber, and after purging the chamber with inert gas, sequentially performing the steps of:
- a) precleaning and passivating the substrate surface by exposure to a reactive fluorine species;
- b) purging the chamber with an inert gas;
- c) depositing silicon carbide by pyrolysis a reactant gas mixture comprising a source of silicon and carbon, and an inert gas;
- d) purging the chamber with an inert gas;
- e) exposing the deposited silicon carbide to the reactive fluorine species thereby passivating exposed surfaces of silicon carbide with fluorine;
- and,
- repeating steps b) to e) until a layer of a desired thickness of silicon carbide has been deposited;
- and,
- subsequently annealing the layer of silicon carbide, thereby incorporating fluorine therein.
A method of forming silicon carbide for an integrated circuit, comprising:
- exposing a surface of a substrate of an integrated circuit in a chemical vapour deposition chamber, and after purging the chamber with inert gas, sequentially performing the steps of:
- a) pre-cleaning and preparing the substrate surface by exposure to a reactive fluorine containing gas;
- b) purging the chamber with an inert gas;
- c) providing a layer of doped silicon carbide on the substrate surface by a method of chemical vapour deposition from a mixture of reactant gases comprising a source of silicon and carbon derived from a volatile liquid phase precursor and a source of a dopant species, and an inert gas;
- d) purging the chamber with the inert gas to remove the reactant gases;
- e) exposing the deposited silicon carbide to said reactive fluorine containing gas thereby passivating exposed surfaces of silicon carbide with fluorine;
- and
- then sequentially repeating the steps b) to e) until a desired thickness of silicon carbide has been deposited, thereby incorporating fluorine into the silicon carbide.
Dependencies are inferred from the claim text.