Loading patent…
AssigneeSextant Avionique
InventorsMichel Ducateau, Jean-Marie Sers
Estimating the term…
A device for enhancing the performance of a real time executive kernel associated with a multiprocessor structure possibly comprising a large number of processors comprises a real time operator behaving, as seen from the processor of the structure, like a memory area. The real time operator sends and receives data to be processed, generates communication control signals and manages the real time context of the processors of the structure. It comprises a plurality of identical hardwired real time operator circuits accessible simultaneously by the processors of the structure but each associated with one only of said processors. The device can be used even if the structure comprises a large number of processors.
Device for optimizing the performance of a real time executive kernel in a multiprocessor structure comprising one or more processors, said device comprising a real time operator behaving, as seen from a processor of said structure, as a memory area and comprising means for sending and for receiving data to be processed, means for generating communication control signals, means for associating with objects managed by a kernel, especially tasks, each having a state, hardware and software events, resources and time, a series of primitives one primitive at a time to manage a clock resource and active resources, means for managing a real time context of said processors of said structure on the basis of a predetermined strategy by means of a scheduler, said scheduler being adapted in particular to activate the tasks cyclically, means for marking waits on timers, means for activating tasks after timers, and means for deciding to change the state of a task to another state on the basis of the primitives of the real time context, wherein said real time operator is organized in a plurality of identical hardwired real time operator circuits, accessible simultaneously by said processors of said structure but each associated with one only of said processors, said circuits being interconnected by a link adapted to transmit an "AGREED" signal ensuring that said real time operator executes only one primitive at a time, each real time operator circuit comprising a scheduler which manages the tasks of only the processor associated with it and global resources and events of the real time operator, said scheduler comprising means for activating the tasks cyclically, means for marking waits on timers and means activitating tasks after timers, said real time operator deciding to change the task state on the basis of primitives of the real time context, said device comprising means for commuting each real time operator circuit in one of the following three functioning modes:
Device for optimizing the performance of a real time executive kernel in a multiprocessor structure comprising one or more processors, said device comprising a real time operator behaving, as seen from a processor of said structure, as a memory area and comprising means for sending and for receiving data to be processed, means for generating communication control signals, means for associating with objects managed by a kernel, especially tasks, each having a state, hardware and software events, resources and time, a series of primitives one primitive at a time to manage a clock resource and active resources, means for managing a real time context of said processors of said structure on the basis of a predetermined strategy by means of a scheduler, said scheduler being adapted in particular to activate the tasks cyclically, means for marking waits on timers, means for activating tasks after timers, and means for deciding to change the state of a task to another state on the basis of the primitives of the real time context, wherein said real time operator is organized in a plurality of identical hardwired real time operator circuits accessible simultaneously by said processors of said structure but each associated with one only of said processors, said circuits being interconnected by a link adapted to transmit an "AGREED" signal ensuring that said real time operator executes only one primitive at a time, each real time operator circuit comprising a scheduler which manages the tasks of only the processor associated with it and global resources and events of the real time operator, said scheduler comprising means for activating the tasks cyclically, means for marking waits on timers and means activating tasks after timers, said real time operator deciding to change the task state on the basis of primitives of the real time context each real time operator circuit comprising at least four automatic devices dedicated to the management of specific real time objects, in particular management of eligible tasks awaiting availability of their processor, management of communications with processors, management of timers, cycles and the real time clock, resource queues, all tasks awaiting an event and processing of external interrupts, said automatic devices communicating with each other via buses internal to said real time operator circuit interconnected by a dynamic router under the control of a sequencer included in one of said automatic devices.
Dependencies are inferred from the claim text.