US 5,295,260 A · Memory range monitoring apparatus for a multiprocessor computer system

Abstract

The present invention provides an apparatus for monitoring access by a processor in a computing system to certain defined portions of memory. According to the present invention, the user specifies an address or range of address (the "watchword") in memory to be monitored. Each processor contains hardware which monitors outgoing memory references. If the processor attempts to access the defined portion of memory, the present invention generates a signal which is sent back to the issuing processor to inform it that referenced the watchword in memory. The present invention has several applications. In particular however, the present invention can be used in conjunction with debugging software packages as an aid for debugging user software programs on multiprocessing computer systems. Specifically, the present invention can be used to pinpoint which processor in a multiprocessing computer system accessed the watchword portion of memory. For example, if a processor executed an instruction containing an error, causing improper calculation of a write destination address which resulted in data errors in memory, the present invention can pinpoint precisely which processor in the multiprocessing computer system executed the erroneous instruction, thus pinpointing the erroneous code to within a few instructions. An additional feature of the present invention is that it operates wholly independently and in parallel with the output circuitry of a processor. Thus, no additional levels of logic are introduced into the processor-to-memory path, and as a result the present invention does not adversely impact overall system performance.

Claims17

Dependent claims

A method of isolating faulty program code in a multitasking multiprocessing system comprised of a plurality of processors, comprising the steps of:

(a) identifying a memory range of addresses which are being addressed in error;
(b) setting a watchword lower address corresponding to a base address of the identified memory range;
(c) setting a watchword upper address corresponding to a limit address of the identified memory range;
(d) issuing in each of the plurality of processors memory reference addresses to produce a plurality of memory reference addresses;
(e) receiving the plurality of memory reference addresses;
(f) comparing each memory reference address with the watchword lower address and the watchword upper address;
(g) generating an output signal if in the comparing step (f) a memory reference address is greater than or equal to the watchword lower address and the memory reference address is less than the watchword upper address;
(h) sending the output signal to the processor which issued the memory reference address and interrupting program execution in the processor which issued the memory reference address;
and
(i) reviewing program code executed by the interrupted processor to isolate the faulty program code.

7 more elements

A computer program debugging apparatus for a multiprocessing computer system, comprising:

a plurality of breakpoint circuit means each connected to a write port of a different one of a plurality of processors, each breakpoint circuit means for comparing a write destination address with a watchword range of memory addresses, such that if the write destination address is within the watchword range of memory addresses, the breakpoint circuit means generates an intermediate interrupt signal;
a plurality of enabling circuit means, each connected to a different one of the plurality of the breakpoint circuit means each enabling circuit means for logically combining the intermediate interrupt signal with an interrupt enable signal, such that if the intermediate interrupt signal is set and the interrupt enable signal is set, the enabling circuit means generates an interrupt flag.

Dependencies are inferred from the claim text.

Memory range monitoring apparatus for a multiprocessor computer system

Life of this patent

Memory range monitoring apparatus for a multiprocessor computer system

Life of this patent

Abstract

Claims17