US 5,295,255 AGranted

Method and apparatus for programming a solid state processor with overleaved array memory modules

AssigneeElectronic Professional Services, Inc.

InventorsKenneth A. Malecek, Timothy F. Powell, Jeffrey A. Dobos

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Abstract

A method and apparatus for programming a mass storage device of the type having a plurality of memory word locations. The memory word locations are organized into a plurality of addressable columns and addressable rows, each memory word location capable of storing one byte word in response to at least two programming steps. Each programming step for a selected memory word location requires a predetermined time period before a subsequent programming step can be processed by the selected memory word location. A first programming step is applied to a first memory word location. The first programming step is applied sequentially to other memory word locations while the first programming step is being processed by the first memory word location. A second programming step is applied to the first memory word location while the first programming step is being process by the other memory word locations. The second programming step is sequentially applied to the other memory word locations while the second programming step is being processed by the first memory word location. Also disclosed is a method of erasing such memory and a method for storing and processing bad address locations.

Claims15

Dependent claims

A data recorder comprising:

an interface board having means for connecting said data recorder to a data source, said interface board including a plurality of receiver circuits and a plurality of driver circuits for respectively inputting and outputting data from and to said data source;
a controller broad operatively connected to said interface board, said controller board including a controller for controlling recording of data from said data source, said controller board further including a temporary memory buffer, a nonvolatile memory, a data bus, an address bus, and a control bus connected to said controller, data first received from said data source being initially stored in said temporary memory buffer by said controller;
a flash memory board including a plurality of flash memory devices, each of said flash memory devices being divided into a plurality of word rows, each word row of each of said flash memory devices having a row address with corresponding rows of said plurality of said flash memory devices having a same row address, each of said flash memory devices defining a word column, said flash memory board further including flash memory device address decoder means operatively connected to said controller for decoding an address output from said controller for selecting a desired one of said flash memory devices and row address decoder means for addressing a word row in a selected one of said flash memory devices, each of said flash memory devices having an internal state machine that is responsive to a plurality of programming steps output from said controller including write command and write word, each of said internal state machines requiring a minimum predetermined time period to process said programming steps;
said controller including processor means for (a) providing said write command step to a first of said plurality of said flash memory devices, (b) providing said write command step to a second of said plurality of flash memory devices while said write command step is being process by said first of said plurality of said flash memory devices, (c) addressing a first of said word rows of said first of said plurality of flash memory devices and providing a first data word for recording in said first word row of said first of said plurality of flash memory devices while said write command step is being process by said second of said plurality of said flash memory devices, and (d) addressing a first of said word rows of said second of said plurality of flash memory devices and providing a second data word for recording in said first word row of said second of said plurality of said flash memory devices while said first data word is being processed by said first of said plurality of said flash memory devices.

1 more element

A data recorder comprising:

a plurality of flash memory devices, each of said plurality of said flash memory devices having a plurality of memory word locations capable of storing data in response to a plurality of programming steps applied to said each of said flash memory devices, said programming steps including write command and write word, each of said flash memory devices having an internal state machine requiring a minimum predetermined time period to process said programming steps, each of said flash memory devices being divided into one word column and a plurality of word rows, each word row of each of said flash memory devices having a row address with corresponding word rows of said plurality of said flash memory devices having a same row address;
first means connected to a first of said plurality of said flash memory devices for providing said write command step to said first of said plurality of said flash memory devices;
second means connected to a second of said plurality of said flash memory devices for providing said write command step to said second of said plurality of said flash memory devices while said write command step provided to said first of said plurality of said flash memory devices is being processed;
third means connected to said first of said plurality of said flash memory devices for addressing a first of said word rows of said first of said plurality of flash memory devices and for providing a first data word for recording in said first word row of said first of said plurality of flash memory devices while said write command step provided to said second of said plurality of said flash memory devices is being processed by said second of said plurality of said flash memory devices;
and
forth means connected to said second of said plurality of said flash memory devices for addressing a first of said word rows of said second of said plurality of flash memory devices and for providing a second data word for recording in said first word row of said second of said plurality of said flash memory devices while said first data word is being processed by said first of said plurality of said flash memory devices.

3 more elements

A method of programming a plurality of flash memory devices, each of said plurality of said flash memory devices having a plurality of memory word locations capable of storing data in response to a plurality of programming steps applied to each of said plurality of said flash memory devices, said programming steps including write command and write word, each of said flash memory devices having an internal state machine requiring a minimum predetermined time period to process said programming steps, said method comprising the steps of:

dividing each of said plurality of said flash memory devices into one word column and a plurality of word rows;
assigning each word row of each of said plurality of said flash memory devices a row address with corresponding word rows of said plurality of said flash memory devices having a same row address;
providing said write command step to a first of said plurality of said flash memory devices;
providing said write command step to a second of said plurality of said flash memory devices while said write command step provided to said first of said plurality of said flash memory devices is being processed;
addressing a first of said word rows of said first of said plurality of said flash memory devices and providing a first data word for recording in said first word row of said first of said plurality of said flash memory devices while said write command step provided to said second of said plurality of said flash memory devices is being processed;
and
addressing a first of said word rows of said second of said plurality of said flash memory devices and providing a second data word for recording in said first word row of said second of said plurality of said flash memory devices while said first data word is being processed by said first of said plurality of said flash memory devices.

4 more elements

Dependencies are inferred from the claim text.