Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel

In a digital computer system operably disposed to process two or more instructions in parallel, the combination comprising:

• an instruction processing unit;
• a main memory for storing object code instructions;
• an instruction compounding unit coupled to said main memory for pre-processing a sequence of instructions selected from said main memory as a scalar instruction sequence;
• a cache memory for storing said scalar instruction sequence of said object code instructions;
• a fetch and issue mechanism for fetching and decoding needed object code instructions and for issuing them for execution by said instruction processing unit of the digital computer system during execution of a program by said digital computer system;
• said instruction processing unit including a plurality of execution units which operate in parallel and in a concurrent manner for supporting parallel execution of a group of up to N instructions from a sequence of instructions to be executed by the digital computer system;
• said instruction compounding unit having means for compounding of instructions for execution by said plurality of instruction units for grouping a plurality of instructions in said scalar instruction sequence wherein the size of the grouping is scalable from 1 to N and whereby the compounding of instructions leaves the object code of compounded instructions unaltered and takes a stream of instructions and selectively categorizes adjacent scalar instructions which would otherwise be executed singly for parallel execution and generates a compounded instruction stream as a sequence of tagged instructions and tag information associated with each of the instructions which indicates whether the scalar instruction can be executed singly or executed in parallel by said plurality of execution units as a group of object code instructions when the group of instructions is presented to said instruction processing unit after a fetch and issue of the group of instructions to said instruction processing unit by said fetch and issue mechanism;
• said cache memory being a high speed cache memory coupled to said main memory by said instruction compounding unit for storing into the high speed cache memory said scalar instruction sequence as a compounded stream of categorized and tagged instructions and the associated tag information for the tagged instructions after pre-processing by the instruction compounding unit;
• said fetch and issue unit mechanism being coupled to the cache memory for fetching from the cache memory said scalar instruction sequence as a sequence of adjacent tagged instructions stored therein as needed for program execution along with their associated tag information and for issuing the instructions to the appropriate instruction execution units when an examination of the tag information associated with an instruction fetched from the cache indicates that the tagged instruction may be processed concurrently, and also for issuing instructions to individual functional units when their associated tag information indicates that parallel execution is not possible, the fetch and issue mechanism examining the tag information and decoding instruction operation code fields of an instruction, and based upon such examination and decoding determining which of available functional units is most appropriate for their processing, and sending the instructions to appropriate ones of the functional units for execution.