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AssigneeInternational Business Machines Corporation
InventorsGary Bischoff, Paul J. Milot, Marc Segre, Jeffrey S. Spencer, Leslie R. Wilson
Estimating the term…
Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapter side, regardless of the direction of transfer.
Apparatus for controlling a FIFO buffer to transfer data in a selected direction between a first line and a second line, said buffer having a first transfer mode in which data is transferred from said first line to said second line and a second transfer mode in which data is transferred from said second line to said first line, comprising:
A method of controlling a FIFO buffer to transfer data in a selected direction between a first line and a second line, said buffer having a first transfer mode in which data is transferred from said first line to said second line and a second transfer mode in which data is transferred from said second line to said first line, comprising the steps of:
Apparatus for controlling the transfer of data between first and second processors via a FIFO buffer comprising:
A method of controlling the transfer of data between first and second processors via a FIFO buffer comprising the steps of:
Apparatus for controlling the transfer of data between first and second processors, said first processor generating an address signal indicating an address within a predetermined address space, said apparatus comprising:
Dependencies are inferred from the claim text.