Control voltage generator for surround sound processor

A surround sound processor for reproduction of a sterephonic audio signal on a plurality of loudspeakers surrounding a listening area, said processor comprising at least an input conditioning and matrixing circuit, a directional detector circuit, a servologic circuit and a variable matrixing circuit, said servologic circuit being for imposing variable time constant smoothing on first and second directional information signals derived from said directional detector circuit to obtain first, second, third and fourth control voltage signals for controlling said variable matrixing circuit, said servologic circuit comprising:

• first and second terminals for receiving said first and second directional information signals;
• first and second identical variable resistance elements having a resistance controlled by a modulated pulse train signal applied to a control terminal thereof;
• first and second capacitors for smoothing said first and second directional information signals, respectively, said first and second variable resistance elements being connected between said first and second terminals and one terminal of each of said first and second capacitors respectively, and the other terminal of each of said first and second capacitors being grounded;
• first and second buffer amplifiers for buffering said smoothed first and second directional information signals appearing on said first and second capacitors respectively, and providing at their outputs said first and second control voltage signals respectively;
• first and second inverter amplifiers for inverting said first and second control voltage signals to provide said third and fourth control voltage signals respectively at their outputs;
• first summing full-wave rectifier circuit, connected to said first terminal and the output of said first inverter amplifier and operative to produce at its output a first absolute value signal proportional to the absolute value of the sum of said first directional information signal and said third control voltage signal;
• second summing full-wave rectifier circuit, connected to said second terminal and the output of said second inverter amplifier and operative to produce at its output a second absolute value signal proportional to the absolute value of the sum of said second directional information signal and said fourth control voltage signal;
• a summing amplifier connected to sum said first and second absolute value signals at the outputs of said first and second summing full-wave rectifier circuits;
• a duration stretching circuit for imposing a slow decay time constant on the output of said summing amplifier to produce a resistance control signal;
• and
• a pulse width modulation circuit responsive to said resistance control signal from said duration stretching circuit, for producing a modulated pulse train signal, which is applied to said control terminals of both said first and second variable resistance elements for reducing their resistances in tandem as the magnitude of said resistance control signal increases;
• thereby decreasing said smoothing time constants applied to said first and second directional information signals in response to rapid changes of one or both said directional information signals and increasing said smoothing time constants when said first and second directional information signals are both varying relatively slowly.

A surround sound processor for reproduction of a stereophonic audio signal on a plurality of loudspeakers surrounding a listening area, said processor comprising at least an input conditioning and matrixing circuit, a directional detector circuit, a servologic circuit and a variable matrixing circuit, said directional detector circuit being for producing for audio input signal currents a first and second directional information signal, and comprising two identical circuits, each such identical circuit comprising:

• first and second input terminals for receiving first and second audio signal currents;
• a first operational amplifier whose non-inverting input is grounded, with a first pair of matched diodes connected in antiparallel between its output an its inverting input, its inverting input being connected to said first input terminal;
• a second operational amplifier whose non-inverting input is grounded, with a second pair of matched diodes connected in antiparallel between its output and its inverting input, its inverting input being connected to said second input terminal;
• a third operational amplifier whose non-inverting input is grounded, with a first resistor connected between its output and its inverting input, its inverting input being connected through a second resistor of equal value to said first resistor to the output of said first operational amplifier;
• a fourth operational amplifier whose non-inverting input is grounded, with a third resistor of equal value to said first resistor connected between its output and its inverting input, its inverting input being connected through a fourth resistor of equal value to said third resistor to the output of said second operational amplifier;
• a third pair of matched diodes whose anodes are connected to the outputs of said first and third operational amplifiers respectively and whose cathodes are connected in common to a fifth resistor;
• a fourth pair of matched diodes whose cathodes are connected to the outputs of said second and fourth operational amplifiers respectively and whose cathodes are connected in common to a sixth resistor of equal value to said fifth resistor;
• said fifth and sixth resistors also being connected to a capacitor whose other terminal is grounded, and to a seventh resistor;
• a fifth operational amplifier whose non-inverting input is grounded, having an eighth resistor connected between its output and its inverting input, said seventh resistor also being connected to its inverting input, and its output being connected to an output terminal;
• a first biasing resistor connected from the cathodes of said third pair of matched diodes to a suitable negative supply voltage, for biasing said third matched pair of diodes;
• and
• a second biasing resistor equal to said first biasing resistor, connected from the anodes of said fourth pair of matched diodes to a positive supply voltage of equal magnitude to said negative supply voltage for biasing said fourth pair of matched diodes with an equal current to that provided by said first biasing resistor for biasing said third pair of matched diodes;
• wherein said seventh resistor is of much lower value than said fifth and sixth resistors, so as to prevent significant interaction between the outputs of said second and fourth operational amplifiers, and said capacitor provides with said seventh resistor in parallel with said fifth and sixth resistors a suitable time constant for smoothing the net current received through said fifth and sixth resistors,
• said circuit being operative to provide at its output terminal a voltage proportional to the logarithm of the ratio of the amplitudes of the audio signal currents applied to its first and second input terminals.