Public key encryption and decryption circuitry and method

A method for encrypting and decrypting binary plaintext comprising the steps of:

• (1) generating a single, rectangular binary matrix K for use as a public key and having row identifiers encoded in discrete segments therein, said matrix K generated by multiplying a rectangular matrix T having the row identifiers embedded therein by a non-singular binary matrix M having an inverse M.sup.-1 , said matrix T and said matrix M.sup.-1 utilized as private keys;
• (2) coding binary plaintext into a nonlinear row selector code wherein digits of a particular logic state are row selector digits;
• (3) encrypting a block of binary plaintext data by selecting discrete rows of said matrix K with said row selector digits;
• (4) adding discrete first digits of columns of said rows selected by said selecting digits modulo-2 to produce a block of binary ciphertext;
• (5) decrypting said binary ciphertext by selecting rows of said matrix M.sup.-1 by particular bit states of said ciphertext;
• (6) adding discrete second digits of said selected rows of said matrix M.sup.-1 modulo-2, producing a first intermediate block of ciphertext wherein at least two most significant bits are a first set of the binary plaintext data and which also contains a first said row identifier;
• (7) utilizing said first row identifier to select at least a portion of a first row of said matrix T;
• (8) adding modulo-2 said portion of said first row of said matrix T with said first intermediate block to produce a second intermediate block containing a second set of said binary plaintext data, the second set containing a second said row identifier therein;
• (9) utilizing said second row identifier to select at least a portion of a second row of said matrix T;
• (10) adding modulo-2 said portion of said second row of said matrix T with said second intermediate block to produce a third intermediate block containing a third set of said binary plaintext data, the third set containing a third said row identifier therein;
• and
• (11) successively repeating steps (9) and (10) for N number, where N is a positive integer, of said rows of matrix T, corresponding said row identifiers and said intermediate blocks until the binary plaintext is recovered.

A method for encrypted communications of a text between a station A and a station B wherein said text is encrypted by an encryption method comprising the steps of:

• (1) said station A and said station B each generating a single, rectangular binary matrix K having row identifier digits each of a particular logic state encoded in discrete segments therein, said matrix K generated by multiplying a rectangular matrix T having the row identifier digits embedded therein by a non-singular binary matrix M having an inverse M.sup.-1,
• (2) said station A and said station B exchanging respective said binary matrix K,
• (3) encrypting said text by selecting rows of said matrix M.sup.-1 by particular bit states of said ciphertext;
• (4) adding digits of said rows selected by said particular bit states modulo-2 to produce an intermediate text wherein first two most significant digits thereof are a first set of said row identifier digits,
• (5) utilizing said first set of said row identifier digits to select at least a first portion of a first row of said matrix T,
• (6) adding modulo-2 said first intermediate text, exclusive of said row identifier digits, and said first portion of said first row of said matrix T, exclusive of bit positions of said row identifier digits, to obtain a second intermediate text wherein most significant digits thereof are a second set of row identifier digits,
• (7) utilizing said second set of row identifier digits to select at least a second portion of a second row of said matrix T,
• (8) adding modulo-2 said second second intermediate text, exclusive of said row identifier digits, to said second portion of said second row of said matrix T, exclusive of bit positions of said row identifier digits, to obtain a third intermediate text,
• (9) successively repeating steps 7 and 8 for N number, where N is a positive integer, of iterations thereof until said text is encrypted, producing a first encrypted text,
• (10) coding the encrypted text into a nonlinear row selector code wherein each discrete segment thereof comprises digits of a particular logic state for selecting a particular row of said matrix K of said station B,
• (11) selecting a discrete row of said matrix K of said station B with said digits of a particular logic state,
• (12) adding columnwise said rows of said matrix K selected by said digits of a particular logic state modulo-2 to produce a second encrypted text,
• (13) communicating said second encrypted text to said station B,
• (14) beginning a decryption of said second encrypted text by selecting rows of said matrix M.sup.-1 of station B by particular logic states of said second encrypted text,
• (15) adding columnwise said rows of said matrix K of station B selected by said particular logic states to produce a first intermediate decrypted text wherein two most significant digits thereof are a first set of row identifier digits for said matrix T of said station B and a first portion of said first encrypted text,
• (16) utilizing said first set of said row identifier digits of said matrix T of said station B to select at least a first portion of a first row of said matrix T of said station B,
• (17) adding said first intermediate decrypted text, exclusive of said row identifier digits, modulo-2 with said first portion of said first row of said matrix T of said station B, exclusive of digit positions of said row identifier digits of said matrix T of said station B, to produce a second intermediate decrypted text wherein most significant digit positions thereof are a second set of said row identifier digits for said matrix T and a second portion of said first encrypted text,
• (18) utilizing said second set of said row identifier digits to select at least a second portion of a second row of said matrix T of said station B,
• (19) adding said second intermediate decrypted text, exclusive of said row identifier digits, modulo-2 with said second portion of said second row of said matrix T selected by said second set of said last-named row identifier digits, exclusive of digit positions of said second row identifier digits, to produce a third intermediate decrypted text wherein most significant digit positions are a third set of row identifier digits and a third portion of said first encrypted text,
• (20) sequentially repeating steps 18 and 19 for N-number, where N is a positive integer, of iterations until all portions of said first encrypted text is recovered,
• (21) coding said first encrypted text into a nonlinear row selector code wherein each discrete segment thereof comprises digits of said particular logic state for selecting a particular row of said matrix K of said station A,
• (22) selecting a discrete row of said matrix K of said station A with said last-named digits of said particular logic state,
• (23) adding columnwise said rows of said matrix K of said station A selected by said last named digits of said particular logic state modulo-2 to produce said text.

A method for effecting a first cryptographic transform of binary data comprising the steps of:

• (1) generating a rectangular binary matrix K by multiplying a rectangular matrix T having row identifiers comprising at least two digits of selected logical states embedded in each discrete row therein by a non-singular binary matrix M having an inverse M.sup.-1, said row identifiers utilized in a second cryptographic transform for reversing said first cryptographic transform;
• (2) coding a block of binary data into a segmented, nonlinear row selector code wherein each discrete segment of said code contains a row selector;
• (3) selecting discrete rows of said matrix K in accordance with a particular bit state of each said row selector and;
• (4) adding columns of selected said rows of said matrix K modulo-2 to produce a block of cryptographically transformed binary data.

A method for effecting a cryptographic transform on a set of binary data which is a product of a rectangular matrix T having a row identifier comprising at least two bits of a selected logic state in each row thereof, and a matrix M, said first set of binary data comprising a series of segments of data, each said segment further containing a discrete row selector each utilized to select a discrete row of a matrix M.sup.-1 and comprising the steps of:

• (1) adding columns of rows of said matrix M.sup.-1 selected by each said row selector, modulo-2, producing a first intermediate block of binary data wherein at least two most significant bits thereof contain a first said row identifier therein;
• (2) utilizing said first row identifier to select at least a portion of a first row of said matrix T ;
• (3) adding modulo-2 said portion of said first row of matrix T with said first intermediate block to produce a second intermediate block containing a second said row identifier therein;
• (4) utilizing said second row identifier to select at least a portion of a second row of said matrix T;
• (5) adding modulo-2 said portion of said second row of said matrix T with said second intermediate block to produce a third intermediate block containing a third row identifier therein;
• and
• (6) successively repeating steps (4) and (5) with successive said row identifiers for N number, where N is a positive integer, of said rows of matrix T, corresponding said row identifiers and said intermediate blocks until the cryptographic transform is complete.

A circuit for generating a cryptographic key comprising:

• a first matrix generator for generating a nonsingular, square matrix;
• a second matrix generator for generating a singular matrix wherein each row contains a plurality of digits where at least two of said digits are discrete row identifiers of predetermined logic state and a remainder of said digits which are not row identifiers;
• and
• combining logic means for combining said singular and nonsingular matrices to form a key matrix.

A circuit for encrypting and decrypting plaintext data and including encryption circuitry comprising:

• encoder circuitry for converting said plaintext data into a row selector code having discrete segments with a row selector in each said segment;
• a first memory storage register having a plurality of first memory locations disposed for storing said row selector code;
• a plurality of first AND gate logic means, one of each responsive to one of each said first memory locations and to a control signal, for selectively passing said row selectors;
• a plurality of first AND gate logic means, one of each responsive to one of each said first memory locations and to a control signal, for selectively passing said row selectors stored in certain ones of said first memory locations as enabling signals;
• a public key storage register containing a public key matrix K and having a plurality of like ordered row and columns of second memory locations corresponding to digit positions of said matrix K, said matrix K generated by combining a nonsingular matrix M with a rectangular matrix T having a row identifier in each discrete row thereof so that matrix K embodies a said row identifier in each discrete row thereof;
• a plurality of second AND gate logic means, one of each responsive to one of each said second memory locations having a said row selector stored therein and to said plurality of first AND gate logic means and arranged in like ordered rows and columns such that discrete rows of said second AND gate logic means associated with said rows of said second memory locations are selectively enabled by said row selectors from said first AND gate logic means, for passing logic levels of rows of said second memory locations to participate in the encryption process;
• a first plurality of X-OR logic means, one of each responsive to one of each of said columns of said second AND gate logic means, for adding said columns of said rows selected by said row selectors modulo-2, producing a binary ciphertext wherein each discrete segment thereof contains a said row identifier, and further including decryption circuitry comprising:
• a second memory storage register having a plurality of third memory locations disposed for storing said ciphertext;
• a plurality of third AND gate logic means, one of each responsive to one of each said memory locations having a said row identifier stored therein and to a control input, for selectively passing each said row identifier as an enabling signal,
• a first private key memory storage register containing a private key matrix M.sup.-1 and having a plurality of like ordered rows and columns of third memory locations corresponding to digit positions of said matrix M.sup.-1,
• a plurality of fourth AND gate logic means arranged in like ordered rows and columns as said third memory locations and responsive to one of each said third memory locations and to one of each said row identifiers from said third AND gate logic means such that each said fourth AND gate logic means are enabled by said row identifiers from said second AND gate logic means, for passing logic levels of selected rows of said third memory locations to participate in the decryption process;
• a second plurality of X-OR logic means, one of each responsive to one of each of said columns of said fourth AND gate logic means, for adding columns of said selected rows of said private key memory storage register modulo-2, producing a first intermediate block of data wherein first two most significant digits thereof are first most significant digits of said plaintext data and further containing a first said row identifier;
• a first decoder responsive to said first two most significant digits of said first intermediate block, for decoding said first row identifier therein and providing a selecting output on one of a first plurality of outputs,
• a second private key memory storage register containing said matrix T and having like ordered plurality of rows of fifth memory storage locations corresponding to rows of said matrix T,
• a plurality of fifth AND gate logic means configured in a plurality of like ordered rows as said rows of said fourth memory storage locations, with each discrete AND gate logic means of said rows of said fifth AND gate logic means each having a first input coupled to one of each said fourth memory storage locations exclusive of two most significant digits thereof, for passing logic levels of a first row of said fifth memory storage locations, exclusive of two most significant digits thereof, selected by said first decoder to participate in the decryption process;
• a third plurality of X-OR logic means, one of each responsive to said first row of said fifth memory storage locations selected by said first decoder and to digit positions of said first intermediate block exclusive of said first two most significant digits thereof, for adding columnwise logic states of said selected first row and said digit positions of said first intermediate block to produce a second intermediate block wherein at least two most significant digit positions of said second intermediate block are second most significant digits of said plaintext data and contain a second row identifier therein;
• a second decoder responsive to said two most significant digit positions of said second intermediate block, for decoding said second row identifier therein and providing a selecting output of one of a second plurality of outputs, one of each of said second plurality of outputs coupled to selected ones of said rows of said plurality of fifth AND gate logic means other than said rows coupled to said first decoder, for selecting a second row of said fifth memory locations;
• a fourth plurality of X-OR logic means, one of each responsive to said second intermediate block exclusive of four most significant digit positions thereof and not coupled to said second decoder, for adding columnwise logic states of said second row, exclusive of said four most significant digits thereof not coupled to said second decoder, for adding columnwise logic states of said second row, exclusive of said second row identifier therein to produce a third intermediate block wherein at least two most significant digit positions thereof are third most significant digits of said plaintext data and contain a third row identifier therein, whereby:
• the above-described process of iteratively adding portions of the intermediate blocks, exclusive of the row identifier therein, modulo-2 with corresponding least significant digit positions of rows of said fifth memory locations each selected in accordance with a decoded said row identifier of corresponding said intermediate blocks is repeated until the plaintext is recovered.

A digital system for generating a cryptographic key for encrypting binary data comprising:

• first digital matrix generation means for generating an invertable digital matrix,
• second digital matrix generation means for generating a noninvertable digital matrix, said noninvertable matrix characterized by selectively arranged sets of digits in each row of said noninvertable matrix and utilized as row identifiers;
• and
• matrix combining means for combining said invertable matrix and said noninvertable matrix and providing a second noninvertable matrix having said row identifiers therein.