Synchronization method for a run length-limited (1,7)-code, and circuit arrangement for said method

A circuit arrangement for performing a synchronization for a run length-limited (1.7)-code with a code rate of 2/3, in which code data bits of a serial data stream are subdivided into two-bit wide data words and transcoded into three-bit wide code words, a sequence of the three-bit wide code words between adjacent ones ("1") comprising at least one zero ("0") but at most seven zeros ("0"), and in which, for the phase-correct decoding of the three-bit wide code words, a given synchronization bit sequence is inserted in the data stream of the code words, characterized in that said arrangement comprises:

• means for recognizing a synchronization sequence in the stream of code words;
• a clock signal generator coupled to receive said stream of code words for deriving a clock signal associated with respect to time with the code words;
• a 3-divider coupled to an output of said clock signal generator for frequency division of said clock signal, said 3-divider being reset by a synchronizing signal generated by said recognizing means;
• a 3/2-divider also coupled to said output of said clock signal generator for frequency division of the clock signal, said 3/2 divider also being reset by the synchronizing signal generated by the recognizing means;
• a series/parallel converter coupled to an output of said recognizing means for series/parallel conversion of serially present code words;
• a first register coupled to an output of said series/parallel converter for buffering parallel present code words from the output of the series/parallel converter under control of a code word clock at an output of the 3-divider;
• a read-only memory coupled to an output of said first register for code conversion of the code words into data words;
• a second register coupled to an output of said read-only memory for buffering the data words supplied by the read-only memory;
• and
• a parallel/series converter coupled to an output of said second register which takes over the buffered data words under control of the code word clock and supplies said data words in a bit-serial form under control of a data word clock at an output of the 3/2-divider.