Clock controller employing a discrete time control loop method for clocking data in an asynchronous channel

In an optical data storage device having a recording channel for recovering data (D) stored as a plurality of signal transitions in said optical data storage device, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F.sub.s, where a normalized clock frequency F.sub.i is defined as the ratio of a synchronous data clock frequency F.sub.d to said sampling clock frequency F.sub.s, where i is a non-zero positive integer and 0.ltoreq.a,b.ltoreq.1, said clock controller comprising:

• output bus means for delivering said recovered data (D);
• input means for receiving a first digital word representing the detection time P.sub.i of an i.sup.th said signal transition;
• first multiplier means coupled to said input means for multiplying said first digital word P.sub.i by a second digital word representing said normalized clock frequency F.sub.i to create a third digital word representing a normalized transition detection value P'.sub.i =P.sub.i F.sub.i ;
• phase error correction means coupled to said first multiplier means for adding said third digital word P'.sub.i to a fourth digital word representing a once-delayed value of a weighted phase error aE'.sub.i-1 to create a fifth digital word representing a corrected transition detection value Z'.sub.i =P'.sub.i +aE'.sub.i-1, said fifth digital word having a rounded integral value representing an i.sup.th said datum D.sub.i =RND(Z'.sub.i), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E'.sub.i =Z'.sub.i -D.sub.i of said normalized transition detection value P.sub.i ;
• and
• output means coupled to said phase error correction means for rounding said fifth digital word Z'.sub.i to create said datum D.sub.i =RND(Z'.sub.i) and for presenting said datum D.sub.i to said output bus means.

In a data storage tape drive having a recording channel for recovering data (D) stored as a plurality of signal transitions in said tape drive media, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F.sub.s, where a normalized clock frequency F.sub.i is defined as the ratio of a synchronous data clock frequency F.sub.d to said sampling clock frequency F.sub.s, where i is a non-zero positive integer and 0.ltoreq.a,b.ltoreq.1, said clock controller comprising:

• output bus means for delivering said recovered data (D);
• input means for receiving a first digital word representing the detection time P.sub.i of an i.sup.th said signal transition;
• first multiplier means coupled to said input means for multiplying said first digital word P.sub.i by a second digital word representing said normalized clock frequency F.sub.i to create a third digital word representing a normalized transition detection value P'.sub.i =P.sub.i F.sub.i ;
• phase error correction means coupled to said first multiplier means for adding said third digital word P'.sub.i to a fourth digital word representing a once-delayed value of a weighted phase error aE'.sub.i-1 to create a fifth digital word representing a corrected transition detection value Z'.sub.i =P'.sub.i +aE'.sub.i-1, said fifth digital word having a rounded integral value representing an i.sup.th said datum D.sub.i =RND(Z'.sub.i), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E'.sub.i =Z'.sub.i -D.sub.i of said normalized transition detection value P.sub.i ;
• and
• output means coupled to said phase error correction means for rounding said fifth digital word Z'.sub.i to create said datum D.sub.i =RND(Z'.sub.i) and for presenting said datum D.sub.i to said output bus means.