A row address decoder and word line driver unit for selectively driving a plurality sets of word lines, word lines respectively selected from said plurality sets of word lines forming in combination a group of word lines so that said plurality sets of word lines being rearranged into a plurality groups of word lines, comprising:
- a) a plurality of row address decoder and word line driver sub-units respectively associated with said plurality sets of word lines, and having
- a-1) a plurality of first address decoder and driver circuits respectively coupled with first common nodes each shared between one of said plurality sets of word lines, and
- a-2) a plurality of second address decoder and driver circuits respectively paired with said plurality of first address decoder and driver circuits, and respectively coupled with second common nodes each shared between one of said plurality sets of word lines at the opposite ends to said first common nodes, said plurality of first address decoder and driver circuits and said plurality of second address decoder and driver circuits being responsive to first address predecoded signals for supplying a word line driving signal to one of said first common nodes and one of said second common nodes, a complementary signal of said word line driving signal being produced by one of said plurality of first address decoder and driver circuits;
- b) a plurality of row address decoder sub-units respectively associated with said plurality groups of word lines, and responsive to second address predecoded signals for producing a gate control signal;
- c) a plurality groups of first transfer transistors of one channel conductivity type respectively associated with said plurality of row address decoder sub-units, and respectively coupled between said first common nodes and said plurality groups of word lines, one of said plurality groups of first transfer transistors indicated by said second address predecoded signals being responsive to said gate control signal for coupling said first common nodes with the associated group of word lines;
- d) a plurality groups of second transfer transistors of said one channel conductivity type respectively associated with said plurality of row address decoder sub-units, and respectively coupled between said second common nodes and said plurality groups of word lines, one of said plurality groups of second transfer transistors indicated by said second address predecoded signals being responsive to said gate control signal for coupling said second common nodes with the associated group of word lines;
- e) a plurality sets of first switching transistors of the opposite channel conductivity type respectively associated with said plurality of first address decoder and driver circuits, and respectively coupled between said plurality sets of word lines and a constant voltage line, one of said plurality sets of first switching transistors being responsive to said complementary signal of said word line driving signal for coupling the associated set of word lines with said constant voltage line;
- and
- f) a plurality groups of second switching transistors of said opposite channel conductivity type respectively associated with said plurality of address decoder sub-units, and respectively coupled between said plurality groups of word lines and said constant voltage line, one of said plurality groups of second switching transistors being responsive to said gate control signal for coupling the associated group of word lines with said constant voltage line.