Dynamic random access memory device with improved power supply system for speed-up of rewriting operation on data bits read-out from memory cells

A random access memory device comprising

• a) a plurality of dynamic memory cells arranged in rows and columns and storing data bits in the form of electric charges, respectively,
• b) a plurality of bit line pairs respectively coupled to the columns of said dynamic memory cells, and propagating small differences in voltage level corresponding to data bits,
• c) a plurality of sense amplifier circuits coupled to said bit line pairs, respectively, and selectively providing first current paths for charging current and second current path for discharging current, thereby increasing said small differences in voltage level on said bit line pairs,
• d) a transfer gate unit coupled between said plurality of dynamic memory cells and said plurality of sense amplifier circuits and operative to isolate said plurality of sense amplifier circuits from said plurality of dynamic memory cells and to interconnect said plurality of sense amplifier circuits and said plurality of dynamic memory cells,
• e) first and second voltage sources coupled in parallel to a bonding pad supplied with a power voltage,
• f) third and fourth voltage sources coupled in parallel to a bonding pad supplied with a ground voltage, and
• g) a plurality of sense amplifier driver circuits divided into first and second driver circuit groups, said plurality of sense amplifier circuits being connectable through said first driver group to said first and third voltage sources and through said second driver group to said second and fourth voltage sources, in which said first driver group interconnecting said first and third voltage sources and said plurality of sense amplifier circuits at a first timing, said transfer gate unit isolating said first bit line sections from said second bit line sections at a second timing after said first timing, said transfer gate unit interconnecting said first bit line sections and said second bit line sections at a third timing after said second timing, said second driver group interconnecting said second and fourth voltage sources and said plurality of sense amplifier circuits at a fourth timing after said third timing.