Row decoding circuit

A row decoding circuit for performing erase operation on at least one word line of a plurality of word lines, comprising first transfer gate means connected to each word line of said plurality of word lines to transfer a prescribed negative dc voltage to word lines selected for an erase operation, second transfer gate means connected to each word line of said plurality of word lines to transfer a first voltage signal to said word lines, third transfer gate means connected to each word line of said plurality of word lines to transfer a prescribed voltage level to said word lines,

• a row decoder for providing a decode signal to select said plurality of word lines,
• a first level shift means for generating said first voltage signal in response to said decode signal, said first voltage signal equaling a read voltage when said plurality of word lines is selected during a read operation, equaling a write voltage when said plurality of word lines is selected during a write operation and equaling said prescribed voltage level when said word lines are not selected during a read operation and during a write operation, said read voltage and said write voltages being the voltages to be applied to a word line to effect the reading and writing processes, and
• a second level shift means for generating a second voltage signal to control switching of said first transfer gate means in response to said decode signal, said second voltage signal equaling a first control voltage capable of causing said first transfer gate means to be turned off when said plurality of word lines is not selected during an erase operation, and equaling a second control voltage capable of causing said first transfer gate means to be turned on when said plurality of word lines is selected during an erase operation, and
• when the reading operating and the writing operation are effected, the gate voltages of said second transfer gate means being set so that second transfer gate means connected to selected word lines is turned on and second transfer gate means connected to unselected word lines is turned off, the gate voltages of said third transfer gate are set so that third transfer gate means connected to selected word lines is turned off and third transfer gate means connected to unselected word lines is turned on to conduct said prescribed voltage level, and
• when an erasing process is effected, the gate voltages of said second and third transfer gate means being set so that second and third transfer gate means are turned off, and said prescribed negative dc voltage for said first transfer gate means connected to selected word lines being set at an erasure voltage and said prescribed negative dc voltages for first transfer gate means connected to unselected word lines being set at said prescribed voltage level, said erasure voltage being a voltage to be applied to a word line said erasing process is to be effected on.