Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory cells arranged in row and column matrix, wherein data may be rewritten to or erased from said memory cells, each row of memory cells has a common source diffused region extending in a specified direction, and at least one common source diffused region has a higher voltage applied thereto during an erase operation than the other common source diffused regions;
• a plurality of word lines, each of which extends in parallel with one of said common source diffused regions and is connected to and shared by the gates of said plurality of memory cells in a row of the array;
• first decoding means for selecting one of said plurality of word lines according to an input address applied to said first decoding means;
• a plurality of first source interconnections composed of a first metal layer electrically connected to said common source diffused regions;
• a plurality of second source interconnections composed of a second metal interconnection layer electrically connected to said first source interconnections, wherein each of said second source interconnections extends in parallel with at least one of said word lines;
• and
• second decoding means for selectively applying a high voltage to one of said plurality of second source interconnection corresponding to the input address and for selectively applying a low voltage to the remaining second source interconnection in an erase operation.

A semiconductor memory device comprising:

• a plurality of memory cell transistors having drain regions, a common source region, and floating gate regions, each said floating gate region overlying a channel region between said common source region and said drain regions;
• a word line extending in a first direction and overlying said floating gate regions;
• a first interlayer insulating film overlying said word line;
• a first metal source interconnection layer extending in a second direction and coupled to said common source region through first contact holes in said first interlayer insulating film;
• metal bit lines extending substantially parallel to each other in the second direction, each said metal bit line coupled to at least one of said drain regions through second contact holes in said first interlayer insulating film;
• a second interlayer insulating film overlying said metal bit lines and said first metal source interconnection layer;
• and
• a second metal source interconnection layer extending in the first direction and coupled to said first metal source interconnection layer through a contact hole in said second interlayer insulating film.

A semiconductor memory device comprising:

• memory cell transistors arranged in a matrix having rows and columns, wherein said memory cell transistors in a predetermined number of rows of the matrix share a common source region;
• word lines respectively coupled to control gates of said memory cell transistors in each row of the matrix;
• metal bit lines respectively coupled to drain regions of said memory cell transistors in each column of the matrix;
• first metal source interconnections, each being coupled to one of said common source regions;
• and
• second metal source interconnections coupled to said first metal source interconnections and extending in the direction of the rows of the matrix.