Integrated circuit with precharged internal data bus
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Estimating the term…
An integrated circuit, such as a memory, having an internal data bus and circuitry for precharging the same is disclosed. Each data conductor in said data bus is associated with a dummy data conductor, which is driven to a complementary logic state from that of its associated data conductor. During precharge and equilibration at the beginning of a cycle, initiated by an address transition detection or by a clock signal, each data conductor is connected to its dummy data conductor so that the data conductor is precharged to a midlevel by way of charge sharing. Also during precharge and equilibration, the data driver is placed in a high impedance state by the sense amplifier output nodes both going to the same logic level. This midlevel precharge allows for faster switching, and reduced instantaneous current, than obtained for rail-to-rail switching. Self-biasing circuits are connected to each of the data conductors and dummy data conductors, to prevent floating conditions during long precharge and equilibration periods. The output stage receiving the data conductor is preferably disabled during precharge and equilibration, so that the data conductor can be precharged near the trip level of the output stage, without risking output stage oscillations. A termination is also provided for the dummy data conductor, matching the load presented by the output stage to the data conductor, so that the data conductor and its dummy data conductor are at complementary states even during transient conditions.
An integrated circuit, comprising:
An integrated circuit comprising:
An integrated circuit, comprising:
A method of operating an integrated circuit, said integrated circuit including functional circuitry coupled to a data bus having a data conductor therein upon which said functional circuitry presents a digital value resulting from an operation by said functional circuitry, said data conductor connected to an output stage, comprising:
A method of operating an integrated circuit, said integrated circuit comprising a memory having a plurality of memory cells, a data bus having a data conductor, said data conductor connected to an output stage, comprising:
Dependencies are inferred from the claim text.