Read/write circuit including sense amplifiers for use in a dynamic RAM

A read/write circuit for use in a dynamic RAM having a plurality of cells connected to a first and second bit lines, and for transferring data from said cells to first and second data bus, or vice versa, said read/write circuit comprising:

• first sense amplifier means comprising first, second, third and fourth transistors connected in series between said first and second bit lines, a gate of said second transistor connected to said second bit line, a gate of said third transistor connected to said first bit line;
• a first junction defined by the connection of said first transistor to said second transistor;
• a second junction defined by the connection of said third transistor to said fourth transistor;
• a gate circuit means connected between said first data bus and said first junction and also connected between said second data bus and said second junction;
• a gate control signal source for providing a gate control signal which opens and closes said gate circuit means;
• and
• a write control signal source for providing a write control signal to a gate of each of said first and fourth transistors,
• whereby during a writing cycle, said gate control signal opens said gate circuit means, and then said write control signal enables said first and fourth transistors to enable access from said first and second data buses to said first and second bit lines, and during a reading cycle, said write control signal disables said first and fourth transistors to produce an amplified bit line data between said first and second junctions, and then said gate control signal opens said gate circuit means to supply said amplified bit line data to said first and second data buses.