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US 5,295,102 AGranted
Semiconductor memory with improved redundant sense amplifier control
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Estimating the term…
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder associated with each column, each of which includes a set of address fuses into which an address is programmed, responsive to which its associated redundant column is to be selected. A plurality of redundant sense amplifiers are each associated with selected redundant columns, and are each controlled to begin the sense operation prior to propagation of the address signal through the redundant column decoders and summing circuitry. In the event that the received memory address does not match any of the programmed values in the redundant column decoders associated with a redundant sense amplifier, the sense operation is terminated. In this way, the sense operation is not delayed by the additional delay required for redundant decoding and propagation of the redundant address signals, and thus the access time penalty for accessing a redundant memory cell is much reduced or eliminated. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each associated redundant column decoder, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.
An integrated circuit comprising a memory, said integrated circuit comprising:
An integrated circuit comprising a memory, said integrated circuit comprising:
An integrated circuit comprising a memory, said integrated circuit comprising:
An integrated circuit comprising a memory, said integrated circuit comprising:
A method of operating a memory in an integrated circuit, said memory including primary and redundant memory cells, a redundant decoder into which a memory address may be programmed responsive to receipt of which a redundant memory cell is to be accessed instead of a primary memory cell, and a redundant read circuit for reading the state of an accessed redundant memory cell and communicating the same externally from the memory cell redundant read circuit dynamically controlled by a read enable signal, comprising:
The method of claim 13, further comprising:
Dependencies are inferred from the claim text.