US 5,295,099 AGranted

Dynamic random access memory device having static column mode of operation without destruction of data bit

AssigneeNEC Corporation

InventorAkihiko Kagami

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Abstract

A dynamic random access memory device comprises memory cells arranged in rows and columns and storing data bits, respectively, bit line pairs respectively coupled to every two columns of the memory cells for propagating the data bits read out from the memory cells, word lines respectively coupled to the rows of the memory cells and allowing the data bits stored in one of the rows of the memory cells to be read out to the bit line pairs, sense amplifier circuits provided in association with the bit line pairs and selectively coupling the component bit lines to first and second sources of voltage level depending upon the logic level of the data bits, a pair of data signal lines coupled to an output data buffer circuit, a column selector unit coupled between the bit line pairs and the data signal lines and sequentially interconnecting the bit line pairs and the data signal lines in a static column mode of operation, and a precharging unit coupled to the data signal lines and having current paths from the first source of voltage level to the data signal lines, wherein a limiter is coupled between the first source of voltage level and the data signal lines and prohibits the data signal lines from undesirable low voltage level so that any data bits on the bit line pairs are never destroyed.

A dynamic random access memory device having a static column mode of operation, comprising:

a) a plurality of memory cells arranged in rows and columns and storing data bits, respectively;
b) a plurality of bit lines respectively coupled to said columns of said memory cells for propagating said data bits read out from said memory cells, every two bit lines being paired with one another so as to form bit line pairs;
c) a plurality of word lines respectively coupled to said rows of said memory cells and allowing said data bits stored in one of said rows of said memory cells to be read out to said bit line pairs, one of said bit lines of each bit line pair propagating said data bit read out from said memory cell therethrough;
d) a plurality of sense amplifier circuits provided in association with said bit line pairs, each of said sense amplifier circuits selectively coupling the bit lines of said associated bit line pair to first and second sources of voltage level depending upon the logic level of said data bit on said associated bit line pair, said first and second sources of voltage level supplying a positive power voltage level and a ground voltage level, respectively;
e) a pair of data signal lines coupled to an output data buffer circuit;
f) a column selector unit coupled between said bit line pairs and said data signal lines and sequentially transferring data bits from said bit line pairs to said data signal lines in said static column mode of operation after one of said word lines allows said data bits to be read out from one of said rows of said memory cells to said bit line pairs;
and
g) a precharging unit coupled to said data signal lines and having current paths from said first source of voltage level to said data signal lines, and a limiter implemented by first and second field effect transistors having respective gate electrodes coupled with said first source of voltage level and coupled between said first source of voltage level and said data signal lines for prohibiting said data signal lines from an excess variation in voltage level when said column selector unit simultaneously couples more than one bit line pair selected from said bit line pairs with said pair of data signal lines in said static column mode of operation, which prevents data bits on said bit line pairs from a change in logic level.

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Abstract

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