Semiconductor memory device having high-speed three-state data output buffer circuit without voltage fluctuation on power voltage lines

A semiconductor memory device fabricated on a single semiconductor chip, comprising:

• a) a memory cell array having a plurality of memory cells arranged in rows and columns, and respectively storing data bits,
• b) a plurality of word lines respectively associated with the rows of said memory cell array, and responsive to an address signal for selectively reading out said data bits from said memory cell array;
• c) a data selecting means coupled with said memory cell array, and responsive to said address signal for selectively transferring said data bits read out from said memory cell array;
• d) a control means supplied with a voltage level at an output data pin, and responsive to variation of said address signal for producing a high-impedance state control signal and either a first or second preceding signal depending upon the voltage level at said output data pin, either of said first or second preceding signals being indicative of an instruction to vary a preceding voltage level of said output data pin to a predetermined point between high and low voltage levels;
• and
• e) a data buffer circuit operative to drive a data pin for supplying a data signal to the outside thereof, and comprising
• e-1) an output inverter coupled with said data pin for driving said data input between said high and low voltage levels,
• e-2) driving means responsive to a data bit on said data selecting means, in the absence of said high-impedance state control signal, for controlling said output inverter, said driving means being further operative to cause said output inverter to enter high-impedance state in the presence of said high-impedance state control signal, and
• e-3) a switching means coupled between said data pin and sources of high and low voltage levels, and responsive to either of said first or second preceding signal for coupling said data pin with one of said sources of high and low voltage levels during said second phase so that said data pin is shifted to said predetermined point before said driving means controls said output inverter with said data bit.