Method of programming electrically erasable programmable read-only memory using particular substrate bias
AssigneeLattice Semiconductor Corporation
InventorGregg R. Josephson
Life of this patent
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Abstract
The apparent voltage used to program an EEPROM cell is increased by applying a negative voltage to the memory control gate of the sense transistor in the cell. This method is applicable to devices in which the substrate is negatively biased.
Claims8
A method of programming an EEPROM cell which includes a sense transistor, said sense transistor being formed in a substrate of a first conductivity type and comprising a first region of a second conductivity type, a second region of said second conductivity type, a floating gate, and a memory control gate, said floating gate being separated from said first region by a layer of dielectric material, the method comprising the steps of:
- biasing said first region to a positive voltage;
- biasing said memory control gate to a negative voltage, thereby causing electrons to tunnel through said layer of dielectric material from said floating gate to said first region;
- and
- lowering the voltage of said substrate to a level less than or equal to the voltage of said memory control gate plus 0.7 volts.
An EEPROM cell comprising:
- a select transistor;
- a sense transistor formed in a substrate of a first conductivity type and comprising
- a first region and a second region of a second conductivity type;
- a memory control gate;
- and
- a floating gate, said floating gate being separated from said first region by a layer of dielectric material, said layer of dielectric material having a thickness designed to permit electron tunneling between said floating gate and said first region when said EEPROM cell is being programmed;
- a means for maintaining said memory control gate at a negative voltage;
- and
- a means for biasing said substrate at a voltage less than or equal to the voltage of said memory control gate plus 0.7 volts.
Dependencies are inferred from the claim text.