Memory circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideshi Miyatake
Life of this patent
Estimating the term…
Abstract
A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.
Claims17
A memory circuit having a memory cell which is connected to a bit line and a word line comprising:
- a read-only signal line for transmitting a signal read out from said memory cell;
- and
- a current-mirror type amplifier disposed between said bit line and said read-only signal line;
- activating means for simultaneously activating said word line and said current-mirror type amplifier.
A memory circuit having a memory cell which is connected to a bit line and a word line comprising:
- a first signal line which is solely available for reading data and transmits a signal read out from said memory cell;
- and
- a current-mirror type amplifier disposed between said bit line and said first signal line;
- a second signal line which is solely available for writing data and transmits a signal to be written in said memory cell;
- and
- a transfer gate which is disposed between said bit line and said second signal line;
- activating means for simultaneously activating said word line and said current-mirror type amplifier.
A memory circuit having a memory cell which is connected to a bit line and a word line comprising:
- a current-mirror type amplifier which is connected to a pair of bit lines;
- a pair of first signal lines which are solely available for reading data and transmit a signal read out from said memory cell;
- a pair of the second signal lines which are solely available for writing data and transmit a signal to be written in said memory cell;
- a column decoder which activates said current-mirror type amplifier and generates a first output in the course of reading mode and a second output in the course of writing mode;
- a first transfer gate which receives said first output from said column decoder and is connected to said pair of the first signal lines;
- and
- a second transfer gate which receives said second output from said column decoder and is connected to said pair of the second signal lines;
- said word line and said current-mirror type and amplifier being simultaneously activated.
Dependencies are inferred from the claim text.