Back to results
US 5,295,079 AGranted
Digital testing techniques for very high frequency phase-locked loops
AssigneeNational Semiconductor Corporation
InventorsHee Wong, Tsun-Kit Chin
Life of this patent
Estimating the term…
Abstract
A digital testing system providing for cost efficient comprehensive testing of very high frequency phase-locked loop performance parameters. The system tests PLL performance parameters both at integrated circuit level and communication board level. Cost efficiency of the testing system allows for volume testing by manufacturers.
Claims20
A digital testing system for testing of very high frequency dynamic phase-locked loop (PLL) performance parameters comprising:
- a PLL with interface means to facilitate communication of a plurality of internal test information;
- a controller means for configuring said PLL as well as extracting and interpreting data from said PLL;
- a communication means for connecting said PLL to said controller means;
- and
- a pattern generator and monitoring means, coupled to said PLL, for generating a plurality of test patterns inputted into said PLL and for monitoring test results outputted from said PLL.
2 more elements
A method for digital testing of very high frequency (VHF) dynamic phase-locked loop (PLL) performance parameters comprising the steps of:
- configuring said PLL in a selected mode through an interface in said PLL;
- applying a digital input pattern to an input terminal of said PLL;
- accessing internal signal information of said PLL through said interface;
- and
- extracting and interpreting said internal signal information with a digital tester via a communication means.
2 more elements
Dependencies are inferred from the claim text.