Test detector/shutoff and method for BiCMOS integrated circuit
AssigneeInternational Business Machines Corporation
InventorsJeanine F. Akiki, Charles W. Hanson
Life of this patent
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Abstract
A test detect and shut off circuit for a BiCMOS integrated circuit is presented. The test detector/shutoff detects the presence of a predetermined test condition in the BiCMOS integrated circuit (IC), and upon detection of the predetermined condition isolates (i.e., switches off) the bipolar circuit portion from the CMOS logic portion of the BiCMOS IC. In this way, bias current in the bipolar transistor circuit is eliminated, thereby facilitating IDD testing of the BiCMOS logic. The detector/shutoff is particularly designed for BiCMOS implementations wherein a single voltage rail supplies voltage V.sub.DD to the logic and bipolar circuit portions of the IC. Corresponding test detect and circuit isolation methods are also presented.
Claims14
A test detect and shut off circuit for facilitating testing of a BiCMOS integrated circuit having a single first power rail supplying operating circuit voltage V.sub.DD and a second power rail supplying intermediate voltage V.sub.TT (wherein under normal integrated circuit operation V.sub.DD >V.sub.TT), said BiCMOS integrated circuit including a logic portion connected between the first power rail supplying voltage V.sub.DD and a ground voltage GND, and a bipolar transistor circuit having multiple current pathways, at least one of said current pathways being connected in parallel with the logic portion between the first power rail supplying voltage V.sub.DD and the ground voltage GND, and at least one of said current pathways being connected between the first power rail supplying voltage V.sub.DD and the second power rail supplying intermediate voltage V.sub.TT, said test detect and shut off circuitry comprising:
- a detect circuit electrically coupled to said BiCMOS integrated circuit for detecting the presence of a predetermined test condition in said BiCMOS integrated circuit and for generating in response thereto a test detect signal;
- and
- a shut off circuit electrically coupled to said BiCMOS integrated circuit and to said detect circuit for opening the at least one bipolar transistor circuit current pathway connected between the first power rail supplying voltage V.sub.DD and ground voltage GND in response to generation of said test detect signal by said detect circuit such that bias current in said at least one bipolar transistor circuit current pathway is eliminated, thereby facilitating testing of the logic portion of said BiCMOS integrated circuit.
A BiCMOS integrated circuit having a test detect and bipolar circuit shutoff for facilitating IDD testing of a logic portion of said BiCMOS integrated circuit, said BiCMOS integrated circuit comprising:
- a single first power input for supplying operating circuit voltage V.sub.DD to said BiCMOS integrated circuit;
- a field effect transistor circuit connected between said first power input supplying voltage V.sub.DD and a ground voltage GND, said field effect transistor circuit comprising said logic portion of said BiCMOS integrated circuit;
- a bipolar transistor circuit having a first circuit portion comprising multiple current pathways connected in parallel with said field effect transistor circuit between said first power input supplying voltage V.sub.DD and said ground voltage GND;
- a second power input for supplying an intermediate circuit voltage V.sub.TT (wherein under normal integrated circuit operation V.sub.DD >V.sub.TT >GND) to a second circuit portion of said bipolar transistor circuit connected between said first power input supplying voltage V.sub.DD and said second power input supplying voltage V.sub.TT ;
- and
- detect/shutoff circuitry coupled to said bipolar transistor circuit for detecting the presence of a predetermined test condition in said BiCMOS integrated circuit, and upon detection of said predetermined test condition for switching off said current pathways of said first circuit portion of said bipolar transistor circuit connected between said first power input supplying voltage V.sub.DD and said ground voltage GND such that quiescent current in said current pathways of said first circuit portion is eliminated, thereby facilitating IDD testing of said logic portion of said BiCMOS integrated circuit.
A method for IDD testing of a logic portion of a BiCMOS integrated circuit, said BiCMOS integrated circuit including a logic transistor circuit and a bipolar transistor circuit, said logic transistor circuit being coupled between a single operating circuit supply voltage V.sub.DD and a ground voltage GND, said bipolar transistor circuit being connected between said supply voltage V.sub.DD and a second intermediate supply voltage V.sub.TT (wherein under normal BiCMOS integrated circuit operation V.sub.DD >V.sub.TT), said testing method comprising the steps of:
- (a) reducing the voltage difference between said operating supply voltage V.sub.DD and said intermediate supply voltage V.sub.TT so as to disable the bipolar transistor circuit connected between said supply voltage V.sub.DD and said supply voltage V.sub.TT ;
- and
- (b) simultaneous with said step (a), conducting IDD testing of said logic transistor circuit, whereby testing of said logic transistor circuit proceeds independent of said bipolar transistor circuit.
Dependencies are inferred from the claim text.