Update synchronizer
AssigneeDigital Equipment Corporation
InventorsRussell Iknaian, Richard B. Watson, Jr.
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Abstract
An update synchronizer includes a two-stage synchronization unit for generating enable signals to select an output signal from among multiple input clock signals of a clock delay multiplexer. The enable signals originate from an asynchronous control signal having a phase different from that of the clock signals. A pre-synchronization logic stage transforms the asynchronous control signal into complementary synchronous control signals for use by the clock synchronization units; these synchronous control signals, in turn, are transformed into complementary selection enable signals having phases within the domains of the input clock signals. This ensures that transitions of the enable signals occur during the same clock period.
Claims6
A synchronizer for generating complementary selection enable signals for enabling a multiplexer to select an output signal from among multiple input clock signals with differing phases, said input clock signals having mostly overlapping assertion levels, said synchronizer comprising:
- means for conditioning said input clock signals to generate a conditioned output signal having an assertion level equal to the combined assertion levels of said input clock signals;
- means for transforming an asynchronous control signal into complementary synchronous control signals in response to said conditioned signal, said asynchronous control signal having a phase different from that of said input clock signals;
- and
- means for transforming said complementary synchronous control signals into said complementary selection enable signals in response to said input clock signals, said complementary selection enable signals having phases within the domains of said input clock signals,
- whereby said complementary selection enable signals for enabling the multiplexer to select said output signal from among said input signals in a manner that avoids interruption of said output signal.
A method for generating complementary selection enable signals for enabling a multiplexer to select an output signal from among multiple input clock signals with differing phases, said input clock signals having mostly overlapping assertion levels, said method comprising the steps of:
- conditioning said input clock signals to generate a conditioned output signal having an assertion level equal to the combined assertion levels of said input clock signals;
- transforming an asynchronous control signal into complementary synchronous control signals in response to said conditioned signal, said asynchronous control signal having a phase different from that of said input clock signals;
- and
- transforming said complementary synchronous control signals into said complementary selection enable signals in response to said input clock signals, said complementary selection enable signals having phases within the domains of said input clock signals,
- whereby said complementary selection enable signals for enabling the multiplexer to select said output signal from among said input signals in a manner that avoids interruption of said output signal.
Dependencies are inferred from the claim text.