High breakdown voltage semiconductor device

A high breakdown voltage semiconductor device comprising:

• a first semiconductor substrate;
• first insulating layer formed on the first semiconductor substrate;
• a second semiconductor substrate bonded to the first semiconductor substrate with the first insulating layer therebetween;
• a first semiconductor region formed in the second semiconductor substrate and isolated at its side by a second insulating layer;
• a second semiconductor region of an n-type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a p-type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the second insulating layer in a manner to be spaced apart from the second semiconductor region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region;
• and
• a fourth semiconductor region of the same conductivity type as that of said first semiconductor region, said fourth semiconductor region being formed at a side of the first semiconductor region in a manner to be located adjacent to said second insulating layer, said first semiconductor region having a doping concentration such that upon application of a predetermined voltage to the second semiconductor region a region between the third semiconductor region and the first insulating layer is filled with a depletion region.

A high breakdown voltage semiconductor device comprising:

• a semiconductor substrate:
• an insulating layer formed on the semiconductor substrate;
• a first semiconductor region formed on the insulating layer and isolated at its side by an isolating region;
• a second semiconductor region of a first conductivity type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a second conductivity type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the isolating region in a manner to be spaced apart from the second semiconductor region and isolating region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region;
• a fourth semiconductor region of the same conductivity type as that of said first semiconductor region, said fourth semiconductor region being formed at a side of the first semiconductor region in a manner to be located adjacent to said isolating region;
• a fifth semiconductor region formed at a bottom of said first semiconductor region and having the same conductivity type as that of said first semiconductor region, said fifth semiconductor region having an impurity concentration which is higher than that of said first semiconductor region;
• and
• a sixth semiconductor region formed at a side of the first semiconductor region in a manner to be located adjacent to said isolating region, said sixth semiconductor region having a lower portion which is continuous with said fifth semiconductor region.

A high breakdown voltage semiconductor device comprising:

• a semiconductor substrate;
• an insulating layer formed on the semiconductor substrate;
• a first semiconductor region formed on the insulating layer and isolated at its side by an isolating region;
• a second semiconductor region of a first conductivity type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a second conductivity type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the isolating region in a manner to be spaced apart from the second semiconductor region and the isolating region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region;
• a fourth semiconductor region of the same conductivity type as that of said first semiconductor region, said fourth semiconductor region being formed at a side of the first semiconductor region in a manner to be located adjacent to said isolating region;
• and
• a fifth semiconductor region of a first conductivity type formed at a side of the first semiconductor region in a manner to be located adjacent to said isolating region.

An insulating gate bipolar transistor comprising:

• a first semiconductor substrate;
• a first insulating layer formed on the first semiconductor substrate;
• a second semiconductor substrate bonded to the first semiconductor substrate with the first insulating layer therebetween;
• a first semiconductor region formed in the second semiconductor substrate and isolated at its side by a second insulating layer;
• a second semiconductor region of an n-type serving as a drain region, formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a p-type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the second insulating layer in a manner to be spaced apart from the second semiconductor region;
• and,
• a fourth semiconductor region of an n-type serving as a source region, formed in the surface region of the third semiconductor region, and having a higher impurity concentration than that of the first semiconductor region, wherein when a predetermined voltage is applied to the third semiconductor region, a region between the third semiconductor region and the first insulating layer is filled with a depletion region.

An insulated gate transistor comprising:

• a semiconductor substrate;
• a first semiconductor region formed in the semiconductor substrate and isolated at its side by an insulating layer;
• a second semiconductor region of an n-type serving as a drain region, formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a p-type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the insulating layer in a manner to be spaced apart from the second semiconductor region;
• and
• a fourth semiconductor region of an n-type serving as a source region, formed in the surface region of the third semiconductor region, and having a higher impurity concentration than that of the first semiconductor region, wherein when a predetermined voltage is applied to the third semiconductor region, a region between the third semiconductor region and the first insulating layer is filled with a depletion region.

An insulated gate bipolar transistor comprising:

• a semiconductor substrate;
• a first semiconductor region formed in the semiconductor substrate and isolated at its side by an insulating layer;
• a second semiconductor region of an n-type serving as a drain region, formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a p-type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the insulating layer in a manner to be spaced apart from the second semiconductor region;
• a fourth semiconductor region of an n-type serving as a source region, formed in the surface region of the third semiconductor region, and having a higher impurity concentration than that of the first semiconductor region;
• and
• a firth semiconductor region of a p-type formed in the surface region of the second semiconductor region.

A high breakdown voltage semiconductor device comprising:

• a first semiconductor substrate;
• a first insulating layer formed on the first semiconductor substrate;
• a second semiconductor substrate bonded to the first semiconductor substrate with the first insulating layer therebetween;
• a first semiconductor region formed in the second semiconductor substrate and isolated at its side by a second insulating layer;
• a second semiconductor region of an n-type formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• and
• a third semiconductor region of a p-type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the second insulating layer in a manner to be spaced apart form the second semiconductor region, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region, wherein when a predetermined voltage is applied to the second semiconductor region, a region between the third semiconductor region and the first insulating layer is filled with a depletion region,
• whereby an electric potential of said second semiconductor region is isolated from that of said second insulating layer.

An insulated gate bipolar transistor comprising:

• a first semiconductor substrate;
• a first insulating layer formed on the first semiconductor substrate;
• a second semiconductor substrate bonded to the first semiconductor substrate with the first insulating layer therebetween;
• a first semiconductor region formed in the second semiconductor substrate and isolated at its side by a second insulating layer;
• a second semiconductor region of an n-type serving as a drain region, formed in a surface portion of the first semiconductor region and having a higher impurity concentration than that of the first semiconductor region;
• a third semiconductor region of a p-type formed in the surface region of the first semiconductor region such that it is located between the second semiconductor region and the second insulating layer in a manner to be spaced apart from the second semiconductor region;
• a fourth semiconductor region of an n-type serving as a source region, formed in the surface region of the third semiconductor region, and having a higher impurity concentration than that of the first semiconductor region, wherein when a predetermined voltage is applied to the third semiconductor region, a region between the third semiconductor region and the first insulating layer is filled with a depletion region,
• whereby an electric potential of said second semiconductor region is isolated from that of the second insulating layer;
• and
• a fifth semiconductor region of a p-type formed in the surface region of the second semiconductor region.

A high breakdown voltage semiconductor device comprising:

• a semiconductor substrate;
• a first insulating layer formed on the semiconductor substrate;
• a semiconductor layer formed on the first insulating layer and isolated at its side by a second insulating layer;
• a first semiconductor region of an n-type formed in a surface portion of the semiconductor layer and having a higher impurity concentration than that of the semiconductor layer;
• and
• a second semiconductor region of a p-type formed in the surface region of the semiconductor layer such that is located between the first semiconductor region and the second insulating layer in a manner to be spaced apart form the first semiconductor region, the second semiconductor region having a higher impurity concentration than that of the first semiconductor layer, wherein when a predetermined voltage is applied to the first semiconductor region, a region between the second semiconductor region and the first insulating layer is filled with a depletion region.