Single-transistor cell EEPROM array for analog or digital storage

A method of storing digital or analog information in an electrically erasable and programmable ROM (EEPROM) storage array, said method comprising the steps of:

• providing a plurality of EEPROM transistors fabricated on a substrate, said EEPROM transistors being arranged in a plurality of rows and columns, each of said EEPROM transistors having spaced-apart drain and source regions in said substrate, and each of said EEPROM transistor having a floating gate and a control gate, said source region of each of said EEPROM transistors being in common with said source region of an EEPROM transistor of an adjacent row of said array, said control gate of each of said EEPROM transistors being electrically connected to said control gate of all other EEPROM transistors of the same respective row of said array, said drain region of each of said EEPROM transistors being electrically connected to said drain regions of all other EEPROM transistors of the same respective column of said array by a single patterned layer of metalization;
• supplying a plurality of operating voltages for use by said EEPROM transistors in said EEPROM storage array, each of said plurality of operating voltages having a voltage above the substrate voltage;
• providing for distribution of said plurality of operating voltages to said source, drain, and control gate of each of said EEPROM transistors, said plurality of operating voltages being used for erasing, programming, or reading from an addressed EEPROM transistor;
• maintaining a net negative charge on said floating gate of said addressed EEPROM transistor after erasing, programming, or reading from said addressed EEPROM transistor, so as to cause the threshold voltage of said addressed EEPROM transistor to always remain approximately one volt above said substrate voltage;
• erasing said addressed EEPROM transistor by inducing an electric field directed from said control gate to said drain of said addressed EEPROM transistor so as to cause said floating gate of said addressed EEPROM transistor to become sufficiently negatively charged so that said threshold voltage of said addressed EEPROM transistor becomes significantly larger than said substrate voltage;
• programming said addressed EEPROM transistor by inducing an electric field directed from said drain to said control gate of said addressed EEPROM transistor so as to cause said floating gate of said addressed EEPROM transistor to bear a net negative charge, said net negative charge being inversely proportional to an analog voltage level being stored in said addressed EEPROM transistor;
• maintaining a sufficiently low electric field between said control gates and said drains of all other EEPROM transistors in said array such that the net negative charge on said floating gates of said all other EEPROM transistors remains equal to the net negative charge that said floating gates of said all other EEPROM transistors bore prior to said programming of said addressed EEPROM transistor;
• and
• reading from said addressed EEPROM transistor by raising said control gate voltage of said addressed EEPROM transistor sufficiently so as to exceed the threshold voltage of said addressed EEPROM transistor, and further raising the operating voltage of said source of said addressed EEPROM transistor so as to cause said drain of said addressed EEPROM transistor to represent a voltage directly proportional to the analog voltage level stored in said EEPROM transistor during said programming.