Method of burning in a semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorTohru Furuyama
Life of this patent
Estimating the term…
Abstract
Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.
Claims40
A method for burning in a semiconductor wafer during a test mode, said semiconductor wafer including chip regions and first wirings connected to said chip regions, each chip region including a circuit, a first circuit line, and a first switch responsive to a first switch voltage for electrically connecting the first circuit line and at least a first one of said first wirings during the test mode, the method comprising the steps of:
- applying a stress voltage to the first one of said first wirings from a voltage source external to said semiconductor wafer;
- and
- applying the first switch voltage to at least a second one of said first wirings from a voltage source external to said semiconductor wafer in order to electrically connect the first one of said first wirings to the first circuit lines of said circuits and thereby stress said circuits.
A method for subjecting a plurality of IC chip regions formed on a semiconductor wafer to a voltage stress test, each of said chip regions including a dynamic type memory circuit operated in a CAS-before-RAS-refresh mode, said semiconductor wafer including two power supply wirings for application of a power supply voltage and a ground potential and two signal wirings for supply of a row address strobe (RAS) signal and a column address strobe (CAS) signal, said two power supply wirings and said two signal wirings being connected in common to each of said dynamic type memory circuits of said chip regions, the method comprising the steps of:
- at the time of the voltage stress test, applying a power supply voltage and a ground potential to said two power supply wirings from the outside of said semiconductor wafer, and
- supplying a CAS signal and a RAS signal in the described order to said two signal wirings.
A method of burning in a semiconductor device, comprising the steps of:
- (a) forming chip regions on a semiconductor wafer, including the steps of forming a circuit in each chip region, forming first circuit lines connected to each circuit, and forming first switches having first terminals connected to a respective one of said first circuit lines an control terminals responsive to a first switch voltage for controlling switching of said first switch;
- (b) forming first wirings on said semiconductor wafer, including the steps of connecting first ones of said first wirings to second terminals of said first switches and connecting second ones of said first wirings to said control terminals of said first switches;
- (c) stressing said circuits of said chip regions by applying a stress voltage thereto, including the steps of applying the stress voltage to said first ones of said first wirings from a first voltage source external to said semiconductor wafer, and applying the first switch voltage to said second ones of said first wirings from a second voltage source external to said semiconductor wafer in order to switch said first switches and electrically connect said first ones of said first wirings to the first lines of said circuits, thereby applying the stress voltage to said circuits via said first circuit lines.
A method of burning in a semiconductor device, comprising the steps of:
- (a) forming chip regions on a semiconductor wafer, including the steps of forming a memory circuit in each chip region, forming word lines connected to each circuit, and forming first switches having first terminals connected to a respective one of said word lines and control terminals responsive to a first switch voltage for controlling switching of said first switches;
- (b) forming first wirings on said semiconductor wafer, including the steps of connecting first ones of said first wirings to second terminals of said first switches and connecting second ones of said first wirings to said control terminals of said first switches;
- and
- (c) stressing said memory circuits of said chip regions by applying a stress voltage thereto, including the steps of applying the stress voltage to said first ones of said first wirings from a first voltage source external to said semiconductor wafer, and applying the first switch voltage to second ones of said first wirings from a second voltage source external to said semiconductor wafer in order to switch said first switches and electrically connect said first ones of said first wirings to said word lines of said memory circuits, thereby applying the stress voltage to said memory circuits via said word lines.
A method of burning in a semiconductor device, comprising the steps of:
- (a) forming chip regions on a semiconductor wafer, including the steps of forming a memory circuit in each chip region, forming word lines connected to each circuit, forming bit lines connected to each circuit, forming first switches having first terminals connected to a respective one of said word lines and control terminals responsive to a first switch voltage for controlling switching of said first switches, and forming second switches having first terminals connected to a respective one of said bit lines and control terminals responsive to a second switch voltage for controlling switching of said second switches;
- (b) forming first wirings on said semiconductor wafer, including the steps of connecting first ones of said first wirings to second terminals of said first switches, connecting second ones of said first wirings to said control terminals of said first switches, and connecting third ones of said first wirings to second terminals of said second switches, and connecting fourth ones of said first wirings to said control terminals of said second switches;
- and
- (c) stressing said memory circuits of said chip regions by applying a stress voltage thereto, including the steps of applying the stress voltage to said first ones of said first wirings from a first voltage source external to said semiconductor wafer, applying the first switch voltage to second ones of said first wirings from a second voltage source external to said semiconductor wafer in order to switch said first switches and electrically connect said first ones of said first wirings to said word lines of said memory circuits, applying the stress voltage to said third ones of said first wirings from a third voltage source external to said semiconductor wafer, applying the second switch voltage to said fourth ones of said first wirings from a fourth voltage source external to said semiconductor wafer in order to switch said second switches and electrically connect said third ones of said first wirings to said bit lines of said memory circuits, thereby applying the stress voltage to said memory circuits via said word lines and said bit lines.
Dependencies are inferred from the claim text.