Digital pressure switch and method of fabrication

A pressure switch, comprising:

• (a) a resilient silicon membrane formed on a first substrate;
• (b) a silicon dioxide insulator, said insulator bonded to said silicon membrane and said first substrate, said insulator electrically isolating said membrane from said first substrate;
• (c) a silicon electrode formed on a second substrate, said electrode bonded to said insulator, said insulator separating said membrane from said electrode;
• (d) a pressure well disposed between said membrane and said electrode;
• and
• (e) a vent extending from said pressure well through said second substrate.

A solid state pressure sensor array, comprising:

• (a) a first silicon substrate having an electrode region;
• (b) a second silicon substrate having a region separated into a plurality of isolated membranes by a plurality of isolation pads, said isolation pads bonded to and extending from said second silicon substrate, said isolation pads bonded to said first silicon substrate, said isolation pads separating said membranes from said electrode region;
• (c) a plurality of membrane contacts, one of each said membrane contacts bonded to a respective one of said plurality of membranes;
• and
• (d) at least one electrode contact bonded to said electrode region.

A method of fabricating a solid state pressure switch, comprising the steps of:

• (a) forming a resilient membrane on a first substrate, said first substrate having first and second surfaces, said membrane coplanar with said first substrate, said membrane electrically isolated from said first substrate by an isolation pad extending from said first surface of said first substrate, said isolation pad forming a well region;
• (b) etching a vent between the surfaces of a second substrate having first and second surfaces;
• and
• (c) bonding said isolation pad to said second substrate, said vent extending into said well region.

A method of fabricating an integrated digital pressure switch array, comprising the steps of:

• (a) etching a plurality of isolation grooves into the first surface of a first substrate having first and second surfaces, said isolation grooves defining polish stops;
• (b) etching a plurality of vents in a second substrate having first and second surfaces, said vents extending between said first and second surfaces of said second substrate;
• (c) depositing an epitaxial layer of thermal oxide on said first surface of said first substrate, said thermal oxide layer extending into said isolation grooves;
• (d) patterning and selectively removing said thermal oxide layer adjacent to said isolation grooves to form a plurality of pressure wells of varying widths between a plurality of isolation pads extending from said first surface of said first substrate;
• (e) grinding said second surface of said first substrate to said polish stops to form isolated membranes between said isolation pads;
• (f) aligning said isolation pads in relation to said vents;
• (g) bringing said isolation pads into physical contact with said second substrate whereby an atomic bond is formed;
• and
• (h) annealing said substrates to strengthen said atomic bond.

A solid state pressure switch fabrication process, comprising the steps of:

• (a) etching an isolation groove into the first surface of a first silicon wafer having first and second surfaces;
• (b) depositing an epitaxial layer of silicon dioxide on said first surface of said first wafer, said silicon dioxide layer extending into said isolation groove;
• (c) etching a vent between the surfaces of a second silicon wafer;
• (d) patterning and selectively removing said silicon dioxide layer to form a pressure well and isolation pad extending from said first surface of said first silicon wafer;
• (e) thinning said second surface of said first wafer to said isolation groove to form a resilient membrane;
• and
• (f) bonding said isolation pad to said second wafer, said vent extending into said pressure well.