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US 5,294,559 AGranted
Method of forming a vertical transistor
AssigneeTexas Instruments Incorporated
InventorSatwinder Malhi
Life of this patent
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Abstract
A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.
Claims7
A method of forming a transistor comprising the steps of;
- forming an isolation layer overlying a semiconductor substrate;
- forming a semiconductor layer of a first conductivity type overlying the isolation layer;
- forming a first doped region of a second conductivity type in the semiconductor layer;
- forming a second doped region of said first conductivity type in said first doped region;
- etching trenches through the semiconductor substrate using the isolation layer as an etch stop;
- and
- filling the trenches with an insulating material.
4 more elements
Dependencies are inferred from the claim text.