Distribution of global variables in synchronous vector processor

A processor device comprising:

• a plurality of N processor elements, each processor element including
• a working register memory;
• an addressable register file memory for storing a plurality of M data words at respective addresses, said respective addresses of said addressable register file memory occupying a first portion of an address space;
• a data register for storing a plurality of L data words at respective addresses, said respective addresses of said data register occupying a second portion of said address space differing from said first portion, said data register of said plural processing elements coupled together for outputting N data words of L bits;
• an arithmetic logic unit connected to said working register, said addressable register file memory and said data register for manipulation of data and transfer of data among said working register memory and an addressed portion of said addressable register file memory or said data register responsive to a received instruction;
• and,
• a multiplexor connected to said working register for selection of the source of data to be written into said working register responsive to said received instruction, said multiplexor of each processing element including connection to said auxiliary register;
• an instruction generator for supplying a common instruction to each of said processing elements including
• an auxiliary register memory for storing a plurality of data words at respective addresses, said respective addresses of said auxiliary register memory occupying a third portion of said address space differing from said first and second portions;
• and
• a global variable distribution circuit coupled to said auxiliary register and each said working register for writing data stored at a respective address within said auxiliary register memory into said working register of each processing element upon supply of an instruction to said processing elements for transfer of data from an address falling within said third portion of said address space;
• said addressable register file memory, working register, register file memory and data register of each processing element storing data words of one bit;
• said multiplexor including a first input for supplying to said working register and a second input for supplying to said working register, said connection between said auxiliary register and said working register of each processing element causing said multiplexor to select said first input for writing into said working register where said addressed data word in said auxiliary register memory is a first value and causing said multiplexor to select said second input for writing into said working register if said addressed data word in said auxiliary register memory is a second value;
• said auxiliary register memory including
• a plurality of multi-bit memories for storing multi-bit data words;
• an auxiliary register memory select circuit for selecting only one of said plural multi-bit memories;
• and
• a data selection circuit for selecting one-bit of a multi-bit data word recalled from said selected multi-bit data memory.