Data processing system which generates a waveform with improved pulse width resolution

A method of using a clock signal to generate a signal waveform having improved pulse width resolution, the clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period, the method comprising the steps of:

• receiving the clock signal;
• receiving a duty control value;
• incrementing/decrementing a count value by 2.sup.N, where N is an integer greater than or equal to zero;
• comparing at least a portion of the duty control value to at least a portion of the count value;
• asserting a match signal when the at least a portion of the duty control value matches the at least a portion of the count value;
• if the duty control value is an integer multiple of 2.sup.N, transitioning the signal waveform from a first logic state to a second logic state when the match signal is asserted;
• and
• if the duty control value is not an integer multiple of 2.sup.N and if the duty control value equals 2.sup.N +1, transitioning the signal waveform from a first logic state to a second logic state one predetermined half-period after the match signal is asserted.

In a data processing system having a clock signal, the clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period, a method of generating a signal waveform using the clock signal, the method comprising the steps of:

• storing a count value, the count value having a least significant bit and a plurality of most significant bits;
• receiving the clock signal;
• receiving a duty control value, the duty control value having a least significant bit and a plurality of most significant bits;
• selecting one of a lower resolution mode and a higher resolution mode;
• if the lower resolution mode has been selected, performing the following steps:
• (a) incrementing/decrementing the count value by ones using the clock signal;
• (b) comparing the duty control value and the count value;
• and
• (c) transitioning the signal waveform from a first logic state to a second logic state when the duty control value matches the count value;
• and
• if the higher resolution mode has been selected, performing the following steps:
• (i) incrementing/decrementing the counter by twos using the clock signal;
• (ii) comparing the plurality of most significant bits of the duty control value to the plurality of most significant bits of the count value;
• (iii) if the duty control value is an even value, transitioning the signal waveform from the first logic state to the second logic state when the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value;
• and
• (iv) if the duty control value is an odd value, transitioning the signal waveform from a first logic state to a second logic state one predetermined half-period after the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value.