Clock distribution apparatus and processes particularly useful in multiprocessor systems

Apparatus for distributing clock pulses from a master clock pulse generator to a system having at least one module which must receive a multiplicity of clock pulses at a multiplicity of clock pulse receiving points for operation of system components in response to arrival of clock pulses at the receiving points within a predetermined maximum time displacement relative to each other comprising:

• a plurality of path establishing means each connected to receive clock pulses from the master clock and having an output connection to a respective clock pulse receiving point, each said path establishing means including elements connected for transferring the clock pulses from the master clock to said respective receiving point, and
• means in at least one of said path establishing means for adjusting the delay of the clock pulses passing therethrough so that the said passing clock pulse arrives at the said output connection of the associated said path establishing means with a time displacement equal to or less than the predetermined maximum time displacement, said adjusting means including an adjustable electrical delay line responsive to control signals input thereto for establishing the amount of delay of the clock pulses passing therethrough, said adjustable electrical delay line including a serial connected network having means for providing a coarse time delay adjustment and means for providing a fine time delay adjustment, said course and fine delay adjustment means each including an input and an output with said input coupled to a plurality of serially coupled elements each having a finite time delay characteristic and a selector circuit responsive to said control signals introduced thereto for coupling signals from at least one of said adjustment means to said adjustment means output, said coarse and fine delay adjustment means each including an input and an output with said input coupled to a plurality of serially coupled elements each having a finite time delay characteristic and a selector circuit responsive to said control signals introduced thereto for coupling signals from at least one of said adjustment means to said adjustment means output, each said plurality of serially coupled elements being configured in a network including
• first and second transistor means with said first transistor means having the base thereof connected to said input and said second transistor means having the emitter-collector circuit thereof coupled to said output,
• a bank of semiconductor elements having their collectors connected in parallel into said emitter-collector circuit of said second transistor, and
• at least one of said semiconductor elements being coupled as a pulse delay stage by including means coupling said element in an emitter follower configuration with the base thereof connected to the collector circuit of said first transistor means,
• whereby the amount of delay for a pulse travelling through said network between said input and output thereof is a function of the number of said semiconductor elements connected in said pulse delay stage configuration.