Random access memory based buffer memory and associated method utilizing pipelined look-ahead reading

A memory device for alternately storing successive data elements which are input to said memory device and for alternately reading out said successive data elements in response to a series of write clock signals and a series of read clock signals, respectively, said successive data elements including an initial data element, a first data element and at least one subsequent data element, said memory device comprising:

• first and second memory arrays each comprising a plurality of memory cells;
• gating logic means for generating an initial data register write signal and an initial data register read signal in response to a first write clock signal and a first read clock signal, respectively, from the series of write clock signals and the series of read clock signals;
• initial data register storing means for storing said initial data element in response to said initial data register write signal and for outputting the stored initial data element in response to said initial data register read signal;
• write cell select means for selecting in response to a first write select signal, said first data element to be stored into a predetermined first cell of one of said first and second memory arrays, and for selecting, in response to a second write select signal, a first subsequent data element of said at least one subsequent data element to be stored into a predetermined first cell of the other of said first and second memory arrays;
• write array select means coupled to said write cell select means for alternately generating said first and second write select signals in response to a second write clock signal and a third write clock signal, respectively, from said series of write clock signals;
• read cell select means for selecting in response to a first read select signal, the first data element stored in the predetermined first cell of said one of said first and second memory arrays to be output therefrom, and for selecting, in response to a second read select signals, the first subsequent data element stored in the predetermined first cell of said other of said first and second memory arrays to be output therefrom;
• read array select means for generating said first and second read select signals in response to said first read clock signal and a second read clock signal, respectively, from said series of read clock signals, said gating logic means being responsive to logic signals output by said read array means to further selectively generate first and second select signals;
• and
• first and second sense amplifier means responsive to said first and second select signals, respectively, for selectively sensing a data element output from a respective one of said first and second memory arrays one of the stored first data element and the stored first subsequent data element being gated to an output means from one of said first and second memory arrays, the gated data element having been previously sensed by the respective one of said first and second sense amplifier means during the previous read clock signal, said output means being coupled to said initial data register storing means and said gating logic means for selectively outputting the initial data element in response to the first read clock signal, for outputting the gated first data element in response to the second read clock signal, and for outputting the gated first subsequent data element in response to a third read clock signal.