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AssigneeUnisys Corporation
InventorsTheodore C. White, Jayesh V. Sheth, Paul B. Ricci, Dan T. Tran
Estimating the term…
A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.
In a computer system having a time-shared bus with a plurality of bus Users coupled to said bus, said plurality of bus Users including a first bus User operative to issue a bus request to said bus to use said bus and to receive a RETRY signal from said bus to retry said bus request, bus lockout prevention apparatus comprising
In a computer system having a time-shared bus with a plurality of bus Users coupled to said bus, said plurality of bus Users including a first bus User operative to issue a bus request to said bus to use said bus and to receive a RETRY signal from said bus to retry said bus request, a bus lockout prevention method comprising
Dependencies are inferred from the claim text.