Apparatus to supplement cache controller functionality in a memory store and a cache memory
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorDavid P. Wright
Life of this patent
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Abstract
A computer comprises a CPU (11), a memory store (12) and a cache comprising a cache memory (17) and a cache controller (16), the CPU (11) being capable of receiving from a memory store (12), or from the cache memory (17), elements of data each arranged as a plurality of words of data associated with a common address, the cache controller (16) inherently only being capable of handling elements of data arranged as a single word of data and an associated address, there being provided a state machine to enable the cache controller (16) to handle elements of data each arranged as a plurality of words of data associated with a common address.
Claims20
A computer comprising a CPU, a memory store connected to a data bus, and a cache comprising a cache memory connected to the data bus and a cache controller, the cache memory and the memory store both being organized and arranged to store a plurality of multiword data elements, each multiword data element being comprised of a plurality of words of data associated with a common address, the CPU having means for receiving and transmitting multiword data elements on the data bus, the cache controller inherently limited to providing cache functionality for single word data elements only, the computer further comprising a state machine connected to the cache controller, the cache memory, and the memory store and having means for supplementing the cache controller to provide functionality for multiword data elements.
A state machine to be used in a memory system comprising a memory store, a cache memory, and a cache controller, the memory store being comprised of a first plurality of multiword data elements and the cache memory being comprised of a second plurality of multiword data elements, the cache controller being inherently limited to providing cache functionality for single word data elements only, said state machine being connected to the cache controller, the cache memory, and the memory store, and having means for supplementing the cache controller to provide functionality for multiword data elements.
A computer comprising a CPU, a memory store connected to a data bus, and a cache comprising a cache memory connected to the data bus and a cache controller, the cache memory and the memory store both being organized and arranged to store a plurality of multiword data elements, each multiword data element being comprised of a plurality of words of data associated with a common address, the CPU having means for receiving and transmitting multiword data elements on the data bus, the cache controller inherently limited to providing cache functionality for single word data elements only, the computer further comprising a state machine connected to the cache controller, the cache memory, and the memory store, said state machine having means for controlling the cache for a remainder of words of a multiword data element after the cache controller has provided functionality for a first word of the multiword data element.
A computer comprising:
- a memory store connected to a data bus, the memory store being organized and arranged to store a first plurality of multiword data elements, each multiword data element being comprised of a plurality of words of data associated with a common address;
- a cache comprising a cache memory connected to the data bus and a cache controller that provides control signals for single word data elements only, the cache memory being organized and arranged to store a second plurality of multiword data elements;
- a CPU, the CPU having means for receiving and transmitting multiword data elements on the data bus;
- and
- a state machine connected to the cache controller, the cache memory, and the memory store, the state machine having means, responsive to the control signals from the cache controller, for controlling the cache memory and the memory store for a remainder of words of a multiword data element after the cache controller has provided control signals for a first word of the multiword data element.
A state machine to be used in a memory system comprising a memory store, a cache memory, and a cache controller, the memory store being comprised of a first plurality of multiword data elements, the cache memory being comprised of a second plurality of multiword data elements, the cache controller providing control signals for single word data elements only, said state machine being connected to the cache controller, the cache memory, and the memory store, and having means, responsive to the control signals from the cache controller, for controlling the cache memory and the memory store for a remainder of words of a multiword data element after the cache controller has provided control signals for a first word of the multiword data element.
Dependencies are inferred from the claim text.