Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path

A cache memory subsystem in a microprocessor-based computer system having a central processor unit (CPU) with a CPU clock, coupled to a CPU bus operating synchronously with the CPU clock, a main memory, a memory bus coupled to the main memory and operating asynchronously with respect to the CPU clock, the cache memory subsystem comprising:

• a) an integrated circuit cache memory comprising:
• i) a read-write cache memory storage array for storing data and having a prescribed data line width;
• ii) a CPU bus interface coupled to the CPU bus for transferring data to and from the CPU bus, and coupled to said read-write cache memory storage array for transferring a full cache storage line of data to and from said cache storage array;
• iii) memory bus interface comprising a plurality of buffer latches coupled to the memory bus for buffering and transferring data to and from the memory bus, and coupled to said cache storage array for transferring data to and from said cache storage array;
• and
• iv) a data path circuit for coupling said CPU bus interface to said memory bus for directly transferring data between said CPU bus interface and said memory bus interface;
• b) a memory bus controller coupled to the CPU and to the memory bus for controlling the memory bus in in response to CPU memory bus requests;
• and
• c) a cache controller coupled to the CPU bus, to the memory bus, to said integrated circuit cache memory storage array, and to said memory bus controller for controlling data transfers to and from the CPU bus, to and from said read-write cache memory storage array, and coordinating with said memory bus controller data transfers to and from the memory bus.