Processing system including memory selection of multiple memories and method in an interrupt environment

A processing system comprising:

• processor means for executing program instructions, said
• processor means including means for generating
• address for fetching said program instructions;
• primary memory means, coupled to said processor means, for
• storing a first set of program instructions including a first set of execution program instructions and a plurality of transition program instructions, and for providing said processor means with said first set of program instructions;
• secondary memory means, coupled to said processor means, for storing a second set of program instructions including a second set of execution program instructions and said plurality of transition program instructions, and for providing said processor means with said second set of program instructions;
• wherein each of said plurality of transition program instructions in said primary memory means has a corresponding transition program instruction in said plurality of transition program instructions in said secondary memory means, each transition program instruction in said primary memory means belong stored in said primary memory means at a selected address, said corresponding transition program instruction in said secondary memory means being stored at an address in said secondary memory means identical to said selected address;
• and
• control means, coupled between said processor means and said primary and secondary memory means, for selecting either said primary memory means or said secondary memory means, said control means being responsive to a select-primary address generated by said processor means for selecting said primary memory means, said control means being responsive to a select-secondary address generated by said processor means for selecting said secondary memory means, said select-primary address being different than said select-secondary address,
• said processor means being responsive to said transition program instructions fetched from one of said primary memory means and said secondary memory means for generating one of said select-primary address and said select-secondary address to cause said control means to select the other one of said primary memory means and said secondary memory means when the execution of execution program instructions by said processor means requires the fetching of execution program instructions from said other one of said primary memory means and said secondary memory means, and
• said control means including latch means for maintaining an identification of which of said primary memory means and said secondary memory means is selected.