Circuit with predetermined delay for selectively relaying interrupt signals through a daisy-chain of linked modules upon removal of a module from a slot

A computer comprising a plurality of disconnectable plug-in modules, including a first module, subsequent modules including a second module and preceding modules including a third module, at plug-in locations of the computer, a bus connecting the modules to one another, the bus including a daisy-chained acknowledging signal line for carrying an acknowledging signal between the modules, means associated with each of said modules for and operatively associated with a single one of said modules for relaying said signal past its associated module if the signal is intended for said subsequent modules, a decoding circuit on each one of said modules for preventing a further relaying of the signal by the first module if the signal is intended for the first module, the means for relaying and the decoding circuit of the first module processing the acknowledging signal within a predetermined response time, a holding circuit associated with a corresponding one of said modules at the plug-in location for said corresponding module, said holding circuit having an input connected said acknowledging signal line and activated in response to a disconnection of the corresponding module from its plug-in location;

• and means in the holding circuit for forwarding the acknowledging signal along the acknowledging signal line when a delay forming an individual lag time for the corresponding module, a sum of said individual lag times for said modules at all said plug-in locations being a total lag time, said total lag time being less than the predetermined response time.