Testing system of computer by generation of an asynchronous pseudo-fault
AssigneeNEC Corporation
InventorsIsao Hasegawa, Atsushi Takahashi
Life of this patent
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Abstract
The testing system is provided with a diagnostic processing apparatus which is independent from a computer to be tested. The diagnostic processing apparatus operates based on a clock signal which is separate from another clock signal used in the computer to asynchronously issue a fault generation command to the computer. The computer is provided with a register for storing particular fault mode information. The computer is responsive to the issued fault generation command for enabling the stored fault mode information so as to generate an asynchronous pseudo-fault in the computer for testing purpose.
Claims16
A testing system of a computer, comprising:
- (A) a diagnostic processing apparatus independent from a computer to be tested including fault setting means for providing a fault generation command to the computer, operative based on a first clock signal separate from a second clock signal used in the computer;
- and
- (B) a computer, including:
- (1) fault information holding means for holding fault mode information representative of a pseudo-fault location in the computer, set by the diagnostic processing apparatus;
- and
- (2) fault enabling means responsive to the fault mode information, for generating an asynchronous pseudo-fault in the computer based on the fault mode information, for use in testing the computer.
A testing system of a computer, comprising:
- (A) a diagnostic processing apparatus operative based on a first clock signal, including:
- (1) fault setting means for issuing a fault generation command;
- (2) a first clock resource for issuing the first clock signal;
- (B) a computer connected to the diagnostic processing apparatus, including:
- (1) a second clock source separate from the first clock source, for issuing a second clock signal;
- (2) a firmware control unit having a synchronous pseudo-fault generating function, synchronous with the second clock signal;
- (3) a fault enabling bit latch connected to an output of the firmware control unit;
- (4) a logical-OR gate connected to an output of the fault enabling bit latch, responsive to the fault generation command;
- and
- (5) a fault information register with fault mode information indicating a given pseudo-fault, responsive to the diagnostic processing apparatus.
A method of testing a computer system, comprising the steps of:
- (A) providing a fault generating command to a computer from a diagnostic processing apparatus independent from the computer to be tested, based on a first clock signal separate from a second clock signal used in the computer;
- (B) holding fault mode information representative of a pseudo-fault location in the computer in a fault information holding means in the computer, set by the diagnostic processing apparatus;
- (C) enabling the held fault mode information responsive to the fault generation command, and generating an asynchronous pseudo-fault in the computer based on the fault mode information, for use in testing the computer.
Dependencies are inferred from the claim text.