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US 5,293,563 AGranted
Multi-level memory cell with increased read-out margin
AssigneeSharp Kabushiki Kaisha
InventorYoshiji Ohta
Life of this patent
Estimating the term…
Abstract
A dynamic semiconductor memory device for storing a signal corresponding to two bits of digital data in a single memory cell. A memory cell consisting of two transistors and one capacitor is formed. Logic is provided to convert two bits of data to two levels of charge with two different polarities. The result is a memory device which requires only 11/2 elements per bit of storage in contrast to the two elements per bit of storage needed in conventional memory cells.
Claims9
A dynamic semiconductor memory device, comprising:
- first and second data line pairs, wherein each data line pair comprises first and second data lines, said first and second data lines being complementary to each other,
- a word line;
- first, second and third bit line pairs, wherein each bit line pair comprises first and second bit lines, said first and second bit lines being complementary to each other;
- a memory cell connected to the word line and the first bit line pair, wherein the memory cell comprises a storage capacitor and first and second selecting means for electrically connecting, under control of the word line, the storage capacitor to the first and second bit lines of said first bit line pair;
- read-out means for reading data stored in said memory cell, wherein the read-out means comprise a first UP line, first and second signal line pairs, first and second capacitors and first and second field-effect transistors, wherein each signal line pair comprises first and second signal lines, said first and second signal lines being complementary to each other, wherein a gate of said first and second field-effect transistors is connected to the second and first signal lines, respectively, of said first signal line pair, wherein a first terminal of said first and second capacitors is electrically connected to the first and second signal lines, respectively, of the second signal line pair, and wherein a second terminal of said first and second capacitors is electrically connected through source-drain paths of said first and second field-effect transistors, respectively, to the first UP line;
- switching means, connected to said first and second bit line pairs and said first and second signal line pairs, for temporarily electrically connecting said first bit line pair to said first signal line pair and said second bit line pair to said second signal line pair;
- equalization means for equalizing the first and second bit line of the first and second bit line pairs, wherein the equalization means comprise a transmission gate formed by connecting first and second field-effect transistors to the first and second bit lines of said first and second bit line pairs;
- a first sense amplifier connected to said first data line pair and said first signal line pair;
- a second sense amplifier connected to said second data line pair and said second signal line pair;
- and
- write-in means, connected to said first, second and third bit line pairs, for electrically connecting said first, second and third bit line pairs during a write operation.
8 more elements
A method of reading two bits of digital data from a single memory cell in a dynamic memory device, wherein the dynamic memory device comprises a memory cell having a storage capacitor with a stored charge;
- a first bit line pair connected to the memory cell, wherein the first bit line pair comprises a first and a second bit line;
- a second bit line pair comprising a first and a second bit line;
- read-out means for reading data stored in the memory cell, wherein the read-out means comprises first and second signal line pairs, each signal line pair having a first and a second signal line;
- a switch connecting the first bit line pair to the read-out leans;
- and first and second sense amplifying means, connected to the read-out means, for amplifying a first potential difference between the first and second signal lines of the first signal line pair and a second potential difference between the first and second signal lines of the second signal line pair, the method comprising the steps of:
- equalizing the first and second bit lines of the first bit line pair;
- electrically connecting said storage capacitor to the first and second bit lines of said first bit line pair so as to distribute the charge stored on the storage capacitor on said first and second bit lines;
- electrically connecting the first and second bit lines of the first bit line pair to the first and second signal lines, respectively, of the first and second signal line pairs;
- adding a differential voltage to one of the signal lines of the second signal line pair;
- and
- converting the first and second potential differences to first and second differential digital data bits, respectively.
8 more elements
A method of writing two bits of digital data to a single memory cell in a dynamic memory device, wherein the dynamic memory device comprises a memory cell including a storage capacitor;
- first, second and third bit line pairs, wherein each bit line pair comprises complementary first and second bit lines and wherein the first bit line pair is connected to the memory cell;
- data switching means connected to the first and second bit line pairs for applying first and second differential digital signals to the first and second bit line pairs, respectively;
- first and second data line pairs, coupled through the data switching means to the first and second bit line pairs, respectively, wherein each data line pair comprises complementary first and second data lines;
- and write-in means, connected to said first, second and third bit line pairs, for electrically connecting said first, second and third bit line pairs during a write operation, wherein the write-in means comprise first write switching means for electrically connecting the first and second bit line pairs and second write switching means for electrically connecting the first and third bit line pairs, the method comprising the steps of:
- providing a true representation of the first and second digital signals on the first data line of the first and second data line pair, respectively;
- providing a complement representation of the first and second digital signals on the second data line of the first and second data line pair, respectively;
- electrically connecting the first and second bit lines of the first and third bit line pairs, respectively;
- electrically connecting the first and second data line pairs to the first and second bit line pairs, respectively, so as to charge the first and second bit line pairs to voltage levels representative of the first and second digital signals, respectively;
- disconnecting the first and second data line pairs from the first and second bit line pairs;
- electrically connecting the first bit line pair to the second bit line pair so as to form, on the first and second bit lines of the first and second bit line pairs, a potential difference between the first and second bit lines of the first bit line pair representative of the first and second digital signals;
- and
- storing a charge representative of the potential difference in the storage capacitor.
9 more elements
Dependencies are inferred from the claim text.