Multi-state flash EEPROM system using incremental programing and erasing methods

An electrically erasable programmable read only memory (EEPROM) system, comprising:

• a semiconductor substrate including an array of a plurality of storage cells arranged in rows and columns across said substrate, said plurality of cells being formed to individually include:
• a source region and a drain region formed in a surface of said substrate with a channel therebetween,
• a floating gate positioned over a first portion of the channel and separated from said substrate surface by a first dielectric layer in a manner that a level of charge on the floating gate controls a level of conductance through the first channel portion, thereby forming a first transistor whose threshold level is controlled by the level of charge on the floating gate,
• a control gate positioned over a second portion of the channel adjacent the first channel portion and separated from said substrate surface by a second dielectric layer, thereby forming a second transistor connected in series with the first transistor, said control gate also extending across the floating gate in a manner that a level of electrical potential on the control gate affects the level of conductance of both of the first and second transistors through the respective first and second portions of the channel between the source and drain regions, and
• an erase gate positioned adjacent said floating gate and separated therefrom by a third dielectric layer,
• reading means connectable to an addressed cell within the array of cells for detecting a level of conductance between the source and drain regions of the addressed cell, said reading means includes means for discriminating between a plurality of more than two predetermined threshold levels of the first transistor of the addressed cell wherein at least one of said predetermined threshold levels results from a net positive charge on the floating gate of the first transistor of the addressed cell, the cells of the array having a predetermined number of storage states more than two,
• erasing means simultaneously connectable to the erase gates of storage cells within one of a plurality of distinct blocks of cells in multiple rows and columns of the array for simultaneously reducing an electron charge from the floating gates of cells within said one block by applying thereto a sequence of pulses of increasing magnitude until at least either (a) threshold levels detected by said reading means between said erase pulses in at least a preset proportion of the cells of said one block reach an erased level, or (b) a preset maximum number of erase pulses have occurred, and
• programming means connectable to a selected cell within the array of cells for increasing an electron charge on its floating gate by applying a sequence of programming pulses to the selected cell until at least either (a) a threshold level detected by said reading means between said programming pulses in the first transistor of the selected cell is raised from said erased level to substantially equal a desired one of said more than two predetermined threshold levels, or (b) a preset maximum number of programming pulses has been applied.