Semiconductor memory device having netlike power supply lines

A semiconductor memory device having a memory cell array divided into a plurality of blocks, comprising:

• a plurality of first power supply lines being disposed in a predetermined direction;
• a plurality of second power supply lines being disposed in parallel and between said first power supply lines in said predetermined direction;
• and
• a plurality of column select lines, each being respectively disposed between the first and second power supply lines in said predetermined direction.

A semiconductor memory device having a memory cell array divided into a given number of first blocks in a row direction, each of said first blocks being divided into a given number of second blocks in a column direction, comprising:

• a plurality of first and second power supply lines being alternately disposed between said second blocks in said column direction;
• a plurality of column select lines being disposed over said second blocks in the row direction;
• and
• a plurality of third and fourth power supply lines, each one of the third and the fourth supply lines being disposed between said column select lines in said row direction, and respectively connected to the first and second power supply lines.

A method for fabricating a semiconductor memory device having a netlike power supply lines structure, comprising the steps of:

• forming a plurality of word lines in a first direction on a semiconductor substrate;
• forming an insulation layer on said plurality of word lines;
• forming a plurality of bit lines in a second direction perpendicular to said first direction on said insulation layer;
• forming a plurality of first and second power supply lines in said first direction on said plurality of bit lines, said first power supply lines being spaced-apart from said second power supply lines by a given distance;
• forming a plurality of column selecting lines in said second direction on said plurality of first and second power supply lines;
• and
• alternatively forming a plurality of third and fourth power supply lines in between said column selecting lines in said second direction, and for respectively connecting to said first and second power supply lines.

A semiconductor memory device having a netlike power supply lines structure, comprising:

• a plurality of word lines arranged in a first direction on a semiconductor substrate;
• a plurality of bit lines arranged in a second direction perpendicular to said first direction, said plurality of bit lines being separated and spaced-apart from said plurality of word lines by an insulating layer;
• a plurality of first and second power supply lines arranged in said first direction on said plurality of bit lines, said first power supply lines being separated and spaced-apart from said second power supply lines by a given distance;
• a plurality of column selecting lines arranged in said second direction on said plurality of first and second power supply lines;
• and
• a plurality of third and fourth power supply lines, each disposed in between said column selecting lines in said second direction, and respectively connected to said first and second power supply lines.

A semiconductor memory device having a netlike power supply line structure, comprising:

• a plurality of bit lines arranged in columns on a substrate;
• a plurality of word lines arranged in rows on the substrate;
• a plurality of first and second power supply lines disposed in parallel with said plurality of bit lines;
• and
• a plurality of column select lines arranged in parallel with said plurality of bit lines, each of said column select lines being disposed between said first and second power supply lines.