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US 5,293,499 AGranted
Apparatus for executing a RISC store and RI instruction pair in two clock cycles
AssigneeSun Microsystems, Inc.
InventorEric H. Jensen
Life of this patent
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Abstract
A processor for a SPARC based RISC computer including a central processing unit including a register file having a pair of read ports and a write port, an instruction register for holding an instruction including addresses of registers to be read and written to, a multiplexor, and apparatus for controlling the multiplexor to transfer the address from a write position of the instruction register to the register file such that the information stored in the addressed register is transferred out of the register file through one of the read ports on the clock cycle following a store instruction.
Claims6
In a reduced instruction set computer (RISC) system comprising a first instruction having three read addresses and a second instruction having a read address, a data constant, and a write address, a central processing unit (CPU) for executing said first and second instruction in two clock cycles, said CPU comprising:
- (a) first register means coupled to an instruction issuing unit of said RISC system for receiving said first and second instructions in a first and a second clock cycle as inputs, and in response, storing the first and second read addresses of said first instruction during said first clock cycle, said read address, data constant and write address of said second instruction during said second clock cycle, and the third read address of said first instruction during said first and second clock cycles, and outputting the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle;
- (b) second register means coupled to said first register means for receiving the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle, and in response, outputting a first and a second data output during said first clock cycle, and a third and a fourth data output during said second clock cycle, and storing a data input during said second clock cycle;
- (c) address generation means coupled to said second register means and a memory unit of said RISC system for receiving said first and second data output during said first clock cycle, and in response, generating a memory address for said memory unit during said first clock cycle;
- (d) arithmetic means coupled to said first and second register means for receiving said fourth data output and data constant during said second clock cycle, and in response, generating said data input for said second register means during said second clock cycle, said third data output being received by said memory unit during said second clock cycle.
1 more element
A reduced instruction set computer (RISC) system comprising:
- (a) instruction issuing means for issuing a first instruction having three read addresses and a second instruction having a read address, a data constant, and a write address;
- (b) a central processing unit (CPU) for executing said first and second instruction in two clock cycles, said CPU comprising
- (b.1) first register means coupled to said instruction issuing means for receiving said first and second instructions in a first and a second clock cycle as inputs, and in response, storing the first and second read addresses of said first instruction during said first clock cycle, said read address, data constant and write address of said second instruction during said second clock cycle, and the third read address of said first instruction during said first and second clock cycles, and outputting the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle;
- (b.2) second register means coupled to said first register means for receiving the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle, and in response, outputting a first and a second data output during said first clock cycle, and a third and a fourth data output during said second clock cycle, and storing a data input during said second clock cycle;
- (b.3) address generation means coupled to said second register means for receiving said first and second data output during said first clock cycle, and in response, generating a memory address during said first clock cycle;
- (b.4) arithmetic means coupled to said first and second register means for receiving said fourth data output and data constant during said second clock cycle, and in response, generating said data input for said second register means during said second clock cycle;
- (c) memory means coupled to said address generation means and said second register means for receiving said memory address during said first clock cycle, receiving and storing said third data output in accordance to said previously received memory address during said second clock cycle.
4 more elements
Dependencies are inferred from the claim text.