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AssigneeUnisys Corporation
InventorsTheodore C. White, Jayesh V. Sheth, Dan T. Tran, Paul B. Ricci
Estimating the term…
A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said bus, said plurality of bus Users including first and second bus Users, said first bus User operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instructions, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system;
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said busy said plurality of bus Users including first and second bus Users, said first bus User operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instruction, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system;
In a computer system having a time-shared bus with a plurality of bus Users and a main memory coupled to said bus, said plurality of bus Users including first and second and bus Users, said first bus user operative to issue bus requests to said bus to use said bus and to receive bus grants, granting bus use thereto, said bus requests including a write request to place a WRITE instruction on said bus to write to said main memory at an address specified by said WRITE instruction, said second bus User having a cache memory system for storing words from said main memory, said cache memory system having cache cycle control means for effecting a cache cycle in response to said WRITE instruction, said cache cycle being operative to determine if said cache memory system is storing a word from said main memory from said address specified by said WRITE instruction and to invalidate said word in said cache memory system;
Dependencies are inferred from the claim text.