Data processing system and memory controller for lock semaphore operations
AssigneeInternational Business Machines Corporation
InventorsWan L. Leung, Richard A. Kelley, Leslie F. McDermott
Life of this patent
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Abstract
A local processor is connected to one port of a dual port memory controller. A bus having a BURST signal line is connected to the other port. The memory controller controls access to a local memory. A remote processor can perform a semaphore operation on a semaphore stored in the local memory by translating a LOCK signal from the remote processor into a bus BURST signal that is activated for a period allowing the remote processor to read and modify the semaphore. While the semaphore operation is being performed, the local processor can access the local memory.
Claims10
A data processing system comprising;
- an expansion bus having address lines, data lines, and control lines including a BURST signal line for controlling burst I/O burst data transfers;
- a local processor;
- a remote processor;
- a remote memory having a remote semaphore at a first semaphore address;
- a remote memory controller connected to said remote memory for controlling access to said remote memory;
- first means interconnecting said local processor, said remote processor, said remote memory controller, and said expansion bus, to share said remote memory between said processors;
- said local processor being operative to initiate a first remote lock semaphore operation by generating a first LOCK signal and said first semaphore address;
- bus arbitration means connected to said expansion bus and to said local processor, said bus arbitration means being responsive to said first LOCK signal for arbitrating for use of said expansion bus by said local processor and for generating a BUS WON signal when said local processor has been granted use of said expansion bus;
- first logic means connected to said local processor, said expansion bus, and said bus arbitration means, said first logic means being responsive to said first LOCK signal and to said BUS WON signal to drive an active BURST signal onto said BURST line, said BURST line being used for remote lock semaphore operations as well as for controlling I/O burst data transfers;
- said local processor being further operative, upon being granted use of said expansion bus, to transmit said first semaphore address on said address lines when said BURST signal is active on said burst line;
- said remote memory controller includes memory arbitration means connected to said BURST signal line and being responsive to said active BURST signal and to said semaphore address, to arbitrate and permit said local processor to access said remote memory;
- and
- said local processor being further operative to perform read/modify/write cycles on said remote semaphore, to thereby complete said first remote lock semaphore operation.
A memory controller for use in a data processing system comprising a local memory for storing a first semaphore at a first address, an expansion bus including a burst signal line and address lines for respectively transmitting a BURST signal and ADDRESS signals, a remote memory connected to said expansion bus for storing a second semaphore at a second address, a processor for selectively emitting lock semaphore requests for accessing said first and second semaphores, each lock semaphore request from said processor including a LOCK signal and ADDRESS signals of one of said semaphores, a remote requestor connected to said expansion bus for transmitting lock semaphore requests from said remote requestor to said memory controller for accessing said first semaphore, each lock semaphore request from said requestor including a BURST signal and said first address, said memory controller comprising:
- connecting means for respectively connecting said memory controller to said processor, said expansion bus, and said local memory;
- access control means connected to said connecting means for granting access to said local memory for lock semaphore operations upon said first semaphore in response to lock semaphore requests from said processor that include said first address;
- said access control means including a memory arbiter for receiving lock semaphore requests from said processor and from said remote requestor over said expansion bus, and determining which request will be granted access to said local memory;
- said logic means connected to said processor and to said expansion bus, said logic means being operable, in response to lock semaphore requests from said processor, to access said remote semaphore, and to convert said LOCK signal of each said request into a BURST signal for transmission on said expansion bus.
Dependencies are inferred from the claim text.