US 5,293,489 AGranted

Circuit arrangement capable of centralizing control of a switching network

AssigneeNEC Corporation

InventorsToshiyuki Furui, Naoto Kaji, Gizo Kadaira, Kouji Kinoshita

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Abstract

In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermined port interval, the control circuit controls the switching network with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance. The reference and leading ports may be varied in a time division fashion when a conflict of internal paths otherwise occurs in relation to the port distance.

Claims21

Dependent claims

A memory accessing system, comprising:

a memory including a plurality of memory units;
a switching network for accessing said memory, comprising
a first port set including consecutively numbered input ports,
a second port set including consecutively numbered output ports connected to said memory units, respectively,
ports of one set of said first port set and said second port set including a reference port having a reference port number,
ports of another set of said first port set and said second port set being arranged in a numerical order, and
a plurality of switching units for forming internal paths between said input ports and said output ports for selectively accessing said memory units,
said switching units connecting said ports of said one set to said ports of said another set at a predetermined port interval relative to said reference port,
said switching units forming said internal paths on the basis of a predetermined relationship between said reference port number and said predetermined port interval;
a control circuit for producing a control signal set including a set of control signals based upon said reference port number and said predetermined port interval;
and
delivering means for delivering said control signal set to said switching units independently of said input ports and internal paths;
said control circuit performing concentrated control of said switching network with said control signals to cause said switching network to synchronously operate to simultaneously connect said input ports and said output ports to provide access to said memory units at said input ports.

10 more elements

A memory accessing system, comprising:

a memory including a plurality of memory units;
a switching network for accessing said memory comprising
a first port set including consecutively numbered input ports,
a second port set including consecutively numbered output ports, said output ports being connected to said memory units, respectively,
ports of one set of said first port set and said second port set including a reference port, and
a plurality of switching units responsive to a set of control signals for forming internal paths between said input ports and said output ports for simultaneously connecting all said ports of said one set with a predetermined port interval from said reference port to ports of another set of said first port set and said second port set, said ports of said another set being arranged in numerical order;
and
a control circuit coupled to said switching units for concentratedly delivering said set of control signals to said switching units independently of said input ports and said internal paths, based upon said reference port and said predetermined port interval.

5 more elements

A method of accessing selected addresses of a plurality of memory units of a memory under control by a control circuit, said selected addresses being numbered with a preselected distance between adjacent selected addresses, comprising the steps:

providing a switching network connected to said memory units, said switching network comprising
a first port set of consecutively numbered input ports,
a second port set of consecutively numbered output ports connected to said operational units and
a plurality of switching units connected between said input ports and said output ports;
establishing interval paths between said input ports and said output ports through said switching units by said control circuit;
selecting one port set of said first port set and said second port set, said one port set having a reference port and a predetermined port interval, by said control circuit;
connecting said reference port to ports of another port set of said first port set and said second port set by said switching units;
producing a control signal set based on said reference port and said predetermined port interval by said control circuit;
delivering said control signal set to said switching units independently of said input ports and said interval paths to simultaneously form said internal paths by said control circuit;
operating said switching network by synchronously indicating said input ports and said output ports by said control circuit;
and
subjecting said switching network to concentrated control by said control signal set produced by said control circuit.

9 more elements

Dependencies are inferred from the claim text.