US 5,293,445 A · AGC with non-linear gain for PLL circuits

Abstract

A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and to apply the second frequency to clock the counter when the PLL is operating outside of the predetermined phase difference range.

Claims22

Dependent claims

A circuit for automatically changing the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation, comprising:

a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference;
a counter;
a motor driving circuit for driving said motor in response to the count reached by said counter through the duration of the phase detector output signal;
a source of clock pulses at a first frequency and a second frequency, said second frequency being lower than said first frequency;
a lock range sense circuit to produce a sense signal output that indicates when said PLL is within a predetermined phase difference range;
and a circuit responsive to said sense signal output for selectively applying said first frequency to clock said counter when said PLL is within said predetermined phase difference range, and to apply said second frequency to clock said counter when said PLL is operating outside said predetermined phase difference range.

3 more elements

A circuit for automatically changing the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation, comprising:

a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference;
a counter;
a latch to receive an output count from said counter;
a motor driving circuit for driving said motor in response to the count reached by said counter through the duration of the phase detector output signal;
a source of clock pulses at first and second frequencies, said second frequency being lower than said first frequency;
circuitry to determine the duration of said phase detector output signal and having an output connected to said latch to enable said latch to hold the count reached by said counter through the duration of said phase detector output signal;
a lock range sense circuit connected to receive the output of said latch to produce a lock signal output that indicates when said PLL is within a predetermined phase difference range;
a saturation detector to produce a saturation signal when said counter is in saturation;
and a circuit responsive to said lock signal output for selectively applying said first frequency to clock said counter and responsive to said saturation signal to apply said second frequency to clock said counter.

6 more elements

Dependencies are inferred from the claim text.

AGC with non-linear gain for PLL circuits

Life of this patent

AGC with non-linear gain for PLL circuits

Life of this patent

Abstract

Claims22